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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? direct replacement for bu-61582 and bu-61583 radiation tolerant & radiation hardened versions fully integrated 1553 terminal flexible processor interface 16k x 16 internal ram automatic bc retries programmable bc gap times bc frame auto-repeat intelligent rt data buffering ceramic package multiple ordering options; +5v (only) +5v/-15v +5v/-12v +5v/transceiverless +5v (only, with transmit inhibits) description the bu-63825(925) is a fully hardware & software compatible, direct drop-in replacement for the bu-61582(83). ddc?s bu-63825 space advanced communication engine (sp?ace ii) is a radiation hardened version of the bu-61580 ace terminal. ddc supplies the bu-63825 with enhanced screening for space and other high reliability applications. the bu-63825 provides a complete integrated bc/rt/mt interface between a host processor and a mil-std-1553 bus. the bu-63825 provides functional and software compatibility with the standard bu- 61580 product and is packaged in the same 1.9 square-inch package footprint. as an option, ddc can supply the bu-63825 with space level screen- ing. this entails enhancements in the areas of element evaluation and screening procedures for active and passive elements, as well as the manufacturing and screening processes used in producing the termi- nals. the bu-63825 integrates dual transceiver, protocol, memory man- agement and processor interface logic, and 16k words of ram in the choice of 70-pin dip or flat pack packages. transceiverless versions may be used with an external electrical or fiber optic transceiver. to minimize board space and ?glue? logic, the sp?ace ii terminals pro- vide flexibility in interfacing to a host processor and internal/external ram. all trademarks are the property of their respective owners. ? 2005 data device corporation bu-63825 space level mil-std-1553 bc/rt/mt advanced communication engine (sp?ace ii) terminal make sure the next card you purchase has...
2 data device corporation www.ddc-web.com bu-63825 c-02/06-0 figure 1. bu-63825 block diagram transceiver a ch. a transceiver b ch. b dual encoder/decoder, multiprotocol and memory management rt address 16kx16 shared ram address bus processor and memory interface logic data bus d15-d0 a15-a0 data buffers address buffers processor data bus processor address bus miscellaneous incmd clk_in, tag_clk, mstclr,ssflag/ext_trg rtad4-rtad0, rtadp transparent/buffered, strbd, select, rd/wr, mem/reg, trigger_sel/memena-in, msb/lsb/dtgrt ioen, memena-out, readyd addr_lat/memoe, zero_wait/memwr, 8/16-bit/dtreq, polarity_sel/dtack int processor and memory control interrupt request
3 data device corporation www.ddc-web.com bu-63825 c-02/06-0 table 1. sp?ace ii series specifications parameter min typ max units absolute maximum rating supply voltage logic +5v transceiver +5v -15v -12v logic voltage input range -0.5 -0.5 +0.5 +0.5 -0.5 6.5 7.0 -18.0 -18.0 v cc +0.5 v v v v v receiver differential input resistance x1/x2 (notes 1-6) x3/x6 (notes 1-6) differential input capacitance x1/x2 (no tes 1-6) x3/x6 (notes 1-6) threshold voltage, transformer coupled, measured on stub common mode voltage (note 7) 11 2.5 10 25 0.860 10 k ? k ? pf pf vp-p vpeak transmitter differential output voltage direct coupled across 35 ? , measured on bus transformer coupled across 70 ? , measured on bus output noise, differential (direct coupled) output offset voltage, transformer coupled across 70 ohms rise/fall time 6 18 -250 100 7 20 150 9 27 10 250 300 vp-p vp-p mvp-p, diff mv nsec power supply requirements voltages/tolerances bu-63825/925x0 +5v (logic) bu-63825/925x1 +5v (logic) +5v ( ch. a, ch. b) v a v b bu-63825/925x2 +5v (logic) +5v ( ch. a, ch. b) v a v b logic (note 12) v ih (v cc = 5.5v) mstclr , clock_in, strbd all other inputs v il (v cc = 4.5v) mstclr , clock_in, strbd all other inputs hysteresis mstclr , clock_in, strbd i ih (v cc =5.5v, v in =2.7v) clock_in all other inputs i il (v cc =5.5v, v in =0.0v) clock_in all other inputs v oh (v cc =4.5v, i oh =max) v ol =(v cc =4.5v, i ol =max) i oh (v cc =4.5v)(note 13) i ol = (v cc =4.5v) 4.5 4.5 4.5 -14.25 4.5 4.5 -11.4 3.85 2 0.5 -10 -400 -10 -600 4 5.0 5.0 5.0 -15.0 5.0 5.0 -12.0 5.5 5.5 5.5 -15.75 5.5 5.5 -12.6 1.35 0.8 +10 -20 +10 -60 0.5 -8 8 v v v v v v v v v v v v a a a a v v ma ma w w w w w w w w w w w w w w w w w w w w w w w w w w 0.750 2.1 2.5 2.97 3.77 1.92 2.35 2.84 3.71 1.34 1.57 1.79 2.23 0.50 0.68 1.06 1.45 2.23 0.59 0.92 1.36 2.16 0.28 0.51 0.75 1.22 0.250 0.875 1.22 1.475 2.0 0.86 1.16 1.46 2.06 0.225 0.335 0.600 0.860 1.385 0.290 0.590 0.890 1.490 power dissipation total hybrid bu-63825/925x0 bu-63825/925x1 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-63825/925x2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-63825/925x3/x6 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle hottest die bu-63825/925x0 bu-63825/925x1 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-63825/925x2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-63825/925x3/x6 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle v v ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma 5.5 5.25 190 240 60 108 175 270 240 60 120 185 305 250 355 460 670 5.0 5.0 50 140 30 68 105 180 140 30 80 130 230 4.5 4.75 power supply requirements (cont?d) voltages/tolerances (cont?d) bu-63825/925x3/x6 (+5v only) +5v (logic) +5v ( ch. a, ch. b) current drain (total hybrid) bu-63825/925x0 +5v (logic) bu-63825/925x1 +5v (note 10) -15v idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-63825/925x2 +5v (note 10) -12v idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-63825/925x3/x6 (+5v) (logic, ch. a & ch. b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle units max typ min parameter table 1. sp?ace ii series specifications (cont)
4 data device corporation www.ddc-web.com bu-63825 c-02/06-0 in. (mm) oz (g) 1.9 x 1.0 x 0.215 (48.26 x 25.4 x 5.46) 0.6 (17) physical characteristics size 70-pin dip, flat pack, gull lead weight 70-pin dip, flat pack, gull lead c/w c/w c/w c/w c c c 150 150 +300 7.10 7.82 7.82 12 -55 -65 thermal thermal resistance, junction-to- case, hottest die ( jc ) bu-63825/925x0 bu-63825/925x1 bu-63825/925x2 bu-63825/925x3/x6 operating junction temperature storage temperature lead temperature (soldering, 10 sec.) s s s s s s s s 19.5 23.5 51.5 131 7 2.5 9.5 18.5 22.5 50.5 129.5 668 17.5 21.5 49.5 128 4 1553 message timing completion of cpu write (bc start- to-start of next message) bc intermessage gap (note 8) bc/rt/mt response timeout (note 9) 18.5 nominal 22.5 nominal 50.5 nominal 128.0 nominal transmitter watchdog timeout rt response time (note 11) units max typ min parameter table 1. sp?ace ii series specs (cont) table 1 notes: notes 1 through 6 are applicable to the receiver differential resistance and differential capacitance specifications: (1) specifications include both transmitter and receiver (tied together internally). (2) measurement of impedance is directly between pins tx/rx a(b) and tx/rx a(b) of the sp?ace ii series hybrid. (3) assuming the connection of all power and ground inputs to the hybrid. (4) the specifications are applicable for both unpowered and powered conditions. (5) the specifications assume a 2 volt rms balanced, differential, sinu- soidal input. the applicable frequency range is 75 khz to 1 mhz. (6) minimum resistance and maximum capacitance parameters are guaranteed, but not tested, over the operating range. (7) assumes a common mode voltage within the frequency range of dc to 2 mhz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), referenced to hybrid ground. use a ddc recommended transformer or other transformer that provides an equivalent minimum cmrr. (8) typical value for minimum intermessage gap time. under software control, may be lengthened to (65,535 s minus message time), in increments of 1 s. introduction ddc?s sp?ace ii series of integrated bc/rt/mt hybrids provide a complete, flexible interface between a microprocessor and a mil-std-1553a, b notice 2, mcair, or stanag 3838 bus, implementing bus controller, remote terminal (rt) and monitor terminal (mt) modes. packaged in a single 1.9 square inch 70- pin dip, surface mountable flat pack or gull lead, the sp?ace ii series contains dual low-power transceivers and encoder/decoders, complete bc/rt/mt multiprotocol logic, memory management and interrupt logic, 16k x 16 of shared static ram and a direct, buffered interface to a host processor bus. the bu-63825 contains internal address latches and bidirection- al data buffers to provide a direct interface to a host processor bus. the bu-63825 may be interfaced directly to both 16-bit and 8-bit microprocessors in a buffered shared ram configuration. in addition, the sp?ace ii may connect to a 16-bit processor bus via a direct memory access (dma) interface. the bu-63825 includes 16k words of buffered ram. alternatively, the sp?ace ii may be interfaced to as much as 64k words of external ram in either the shared ram or dma configurations. the sp?ace ii rt mode is multiprotocol, supporting mil-std- 1553a, mil-std-1553b notice 2, and stanag 3838 (including efabus). the memory management scheme for rt mode provides an option for separation of broadcast data, in compliance with 1553b notice 2. both double buffer and circular buffer options are programmable by subaddress. these features serve to ensure data consistency and to off-load the host processor for bulk data transfer applications. the sp?ace ii series implements three monitor modes: a word monitor, a selective message monitor, and a combined rt/selec- tive monitor. other features include options for automatic retries and pro- grammable intermessage gap for bc mode, an internal time tag register, an interrupt status register and internal command ille- galization for rt mode. clock input frequency nominal value (programmable) default mode option long term tolerance 1553a compliance 1553b compliance short term tolerance,1 second 1553a compliance 1553b compliance duty cycle mhz mhz % % % % % 0.01 0.10 0.001 0.01 60 16.0 12.0 -0.01 -0.10 -.001 -0.01 40 table 1 notes (cont) (9) software programmable (4 options). includes rt-to-rt timeout (mid-parity of transmit command to mid-sync of transmitting rt status). (10) for both +5 v logic and transceiver. +5 v for channels a and b. (11) measured from mid-parity crossing of command word to mid-sync crossing of rt's status word. (12) mstclr , clock_in, and strbd are cmos inputs with hystere- sis. remainder are ttl. (13) minus sign indicates direction of current flow.
5 data device corporation www.ddc-web.com bu-63825 c-02/06-0 functional overview transceivers for the +5 v and -15 v/-12 v front end, the bu-63825x1(x2) uses low-power bipolar analog monolithic and thin-film hybrid technology. the transceiver requires +5 v and -15 v (-12 v) only (requiring no +15 v/+12 v) and includes voltage source trans- mitters. the bu-63825x3(x6) utilizes low-power bicmos analog monolithic and thin film hybrid technology as well but requires +5v only. the voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus load- ing. the receiver sections of the bu-63825 are fully compliant with mil-std-1553b in terms of front end overvoltage pro- tection, threshold, common mode rejection, and word error rate. in addition, the receiver filters have been designed for optimal operation with the m-rad chip?s manchester ii decoders. m-rad digital monolithic the m-rad digital monolithic represents the cornerstone ele- ment of the bu-63825 sp?ace ii family of terminals. the m-rad chip is actually a radiation hardened version of ddc?s m? (m- prime) monolithic which is the key building block behind ddc?s non-radiation hardened bu-61580 ace series of terminals. as such, the m-rad possesses all the enhanced hardware and soft- ware features which have made the bu-61580 ace the industry standard 1553 interface component. the m-rad chip consists of a dual encoder/decoder; complete protocol for bus controller (bc), 1553a/b/mcair remote terminal (rt), and monitor (mt) modes; memory management and interrupt logic; a flexible, buffered interface to a host proces- sor bus and optional external ram. reference the region within the dotted line of figure 1. besides realizing all the protocol, memory management, and interface functions of the earlier aim- hy series, the m-rad chip includes a large number of enhance- ments to facilitate hardware and software design, and to further off-load the 1553 terminal?s host processor. decoders the default mode of operation for the bu-63825 bc/rt/mt requires a 16 mhz clock input. if needed, a software program- mable option allows the device to be operated from a 12 mhz clock input. most current 1553 decoders sample using a 10 mhz or 12 mhz clock. in the 16 mhz mode (or 12 mhz), the decoders sample using both clock edges; this provides a sampling rate of 32 mhz or 24 mhz. the faster sampling rate for the m-rad?s manchester ii decoders provides superior performance in terms of bit error rate and zero-crossing distortion tolerance. for interfacing to fiber optic transceivers for mil-std-1773 applications, a transceiverless version of the sp?ace ii can be used. these versions provide a register programmable option for a direct interface to the single-ended outputs of a fiber optic receiver. no external logic is needed. time tagging the sp?ace ii includes an internal read/writable time tag register. this register is a cpu read/writable 16-bit counter with a programmable resolution of either 2, 4, 8, 16, 32, or 64 s per lsb. also, the time tag register may be clocked from an exter- nal oscillator. another option allows software controlled incre- menting of the time tag register. this supports self-test for the time tag register. for each message processed, the value of the time tag register is loaded into the second location of the respective descriptor stack entry (?time tag word?) for both bc and rt modes. additional provided options will: clear the time tag register fol- lowing a synchronize (without data) mode command or load the time tag register following a synchronize (with data) mode command; enable an interrupt request and a bit setting in the interrupt status register when the time tag register rolls over from ffff to 0000. assuming the time tag register is not loaded or reset, this will occur at approximately 4 second time intervals, for 64 s/lsb resolution, down to 131 ms intervals, for 2 s/lsb resolution. another programmable option for rt mode is the automatic clear- ing of the service request status word bit following the bu-63825?s response to a transmit vector word mode command. interrupts the sp?ace ii series components provide many programmable options for interrupt generation and handling. the interrupt out- put pin int has three software programmable modes of opera- tion: a pulse, a level output cleared under software control, or a level output automatically cleared following a read of the interrupt status register. individual interrupts are enabled by the interrupt mask register. the host processor may easily deter- mine the cause of the interrupt by using the interrupt status register. the interrupt status register provides the current state of the interrupt conditions. the interrupt status register may be updated in two ways. in the standard interrupt handling mode, a particular bit in the interrupt status register will be updated only if the condition exists and the corresponding bit in the interrupt mask register is enabled. in the enhanced interrupt handling mode, a particular bit in the interrupt status register will be updated if the condition exists regardless of the contents of the corresponding interrupt mask register bit. in any case, the respective interrupt mask register bit enables an interrupt for a particular condition.
6 data device corporation www.ddc-web.com bu-63825 c-02/06-0 table 2. sp?ace ii series radiation specifications* part number total dose single event upset single event latchup bu-63825(925)x0 bu-63825(925)x1 bu-63825(925)x2 1 x 10 6 rad 2.56 x 10 -5 errors/device-day, (let threshold of 63 mev-cm 2 /mg) immune qci testing mil-std-883, method 1018 mil-std-883, method 1010 condition c and mil-std-883, method 2012 mil-std-883, method 2012 mil-std-883, method 2023 mil-std-883, method 1015 mil-std-883, method 2020 condition a mil-prf-38534 mil-std-883, method 2018 mil-std-883, method 2010 condition a mil-std-750, method 2072 and 2073 mil-std-883, method 2032 class s method moisture content limit of 5000 ppm extended temperature cycling: 20 cycles including radiographic (x-ray) testing radiographic (x-ray) analysis 100% non-destructive wirebond pull (standard on this device) 320-hour burn-in (standard on this device) particle impact noise detection (pind) element evaluation: visual, electrical, wire bondability, 24-hour stabilization bake, 10 temperature cycles 5000 g?s constant acceleration 240-hour powered burn-in and 1000-hour life test (burn-in and 1000-hour life test are only required for active components.) sem analysis for integrated circuits visual inspection: integrated circuits transistors & diodes passive components assembly & test element evaluation table 3. high reliability screening options bu-63825(925)x3 bu-63825(925)x6 100 krad 2.56 x 10 -5 errors/device-day, (let threshold of 63 mev-cm 2 /mg) immune radiation tolerance the bu-63825 combines analog bipolar/bicmos transceivers with logic and ram fabricated to provide radiation survivability. to summarize, bu-63825(925)x0, x1, x2 has a total gamma dose immunity of 1x10 6 rad and a let threshold of 63 mev-cm 2 /mg, provid- ing a soft error rate of 2.56 x 10 -5 errors/device-day. bu-63825(925)x3, x6 has a total gamma dose immunity of 100-k rad and a let threshold of 63 mev-cm 2 /mg, providing a soft error rate of 2.56 x 10 -5 errors/device-day. the hybrids are inherently immune to latchup. the transceiver is bipolar/bicmos, the digital logic is implemented in a honeywell ricmos? iv soi gate array (hx2000 series) and the ram is implemented utilizing a radiation-hardened process (honeywell hx6256). high-rel screening ddc is committed to the design and manufacture of hybrids and transformers with enhanced processing and screening for spaceborne applications and other systems requiring the highest levels of reliability. these platforms include launch vehicles, satellites and the international space station. ddc has tailored its design methodologies to optimize the fabri- cation of space level hybrids. the intent of the design guidelines is to minimize the number of die and wirebonds, minimize the number of substrate layers, and maximize the space between components. ddc?s space grade products combine analog bipo- lar/bicmos and radiation hardened honeywell ricmos? iv soi gate array (hx2000 series) technology to provide various levels of radiation tolerance. the bu-63825 is packaged in a 70-pin ceramic package. in con- trast to kovar (metal) packages, the use of ceramic eliminates the hermeticity problems associated with the glass beads used in the metal packages. in addition, ceramic packages provide more rigid leads, better thermal properties, easier wirebonding, and lower weight. the production of the space level hybrids can entail enhanced screening steps beyond ddc?s standard flow. this includes condition a visual inspection, sem analysis, and element evalu- ation for all integrated circuit die. for the hybrids, additional screening includes particle impact noise detection (pind), 320- *note: radiation parameters specified on this data sheet are derived from initial qualification testing by ddc and published data from asic manufacturers. these devices have not been evaluated for compliance to the rha requirements stipulat- ed in mil-prf-38534, appendix g .
7 data device corporation www.ddc-web.com bu-63825 c-02/06-0 hour burn-in (standard on this device), 100% non-destructive wirebond pull (standard on this device), x-ray analysis, as well as destructive physical analysis (dpa) testing, extended tem- perature cycling for qci testing, and a moisture content limit of 5000 ppm. table 3 summarizes the procurement screening, element evaluation, and hybrid screening used in the production of the bu-63825. addressing, internal registers, and memory management the software interface of the bu-63825 to the host processor consists of 17 internal operational registers for normal operation, an additional 8 test registers, plus 64k x 16 of shared memory address space. the bu-63825?s 16k x 16 of internal ram resides in this address space. reference table 4. definition of the address mapping and accessibility for the sp?ace ii?s 17 nontest registers, and the test registers, is as fol- lows: interrupt mask register: used to enable and disable interrupt requests for various condi- tions. configuration registers #1 and #2: used to select the bu-63825?s mode of operation, and for soft- ware control of rt status word bits, active memory area, bc stop-on-error, rt memory management mode selection, and control of the time tag operation. start/reset register: used for ?command? type functions, such as software reset, bc/mt start, interrupt reset, time tag reset, and time tag register test. the start/reset register includes provisions for stopping the bc in its auto-repeat mode, either at the end of the current message or at the end of the current bc frame. bc/rt command stack pointer register: allows the host cpu to determine the pointer location for the cur- rent or most recent message when the bu-63825 is in bc or rt modes. bc control word/rt subaddress control word register: in bc mode, allows host access to the current or most recent bc control word. the bc control word contains bits that select the active bus and message format, enable off-line self-test, mask- ing of status word bits, enable retries and interrupts, and speci- fy mil-std-1553a or -1553b error handling. in rt mode, this register allows host access to the current or most recent subaddress control word. the subaddress control word is reserved 1 1 1 1 1 1f ? ? reserved 0 0 0 1 1 18 test mode register 7 1 1 1 0 1 17 ? ? test mode register 0 0 0 0 0 1 10 rt bit word register (rd) 1 1 1 1 0 0f rt status word register (rd) 0 1 1 1 0 0e bc frame time/rt last command /mt trigger word register (rd/wr) 1 0 1 1 0 0d bc time remaining to next message register (rd/wr) 0 0 1 1 0 0c bc frame time remaining register (rd/wr) 1 1 0 1 0 0b data stack address register (rd/wr) 0 1 0 1 0 0a configuration register #5 (rd/wr) 1 0 0 1 0 09 configuration register #4 (rd/wr) 0 0 0 1 0 08 configuration register #3 (rd/wr) 1 1 1 0 0 07 interrupt status register (rd) 0 1 1 0 0 06 time tag register (rd/wr) 1 0 1 0 0 05 bc control word/rt subaddress control word register (rd/wr) 0 0 1 0 0 04 bc/rt command stack pointer register (rd) 1 1 0 0 0 03 start/reset register (wr) 1 1 0 0 0 03 configuration register #2 (rd/wr) 0 1 0 0 0 02 configuration register #1 (rd/wr) 1 0 0 0 0 01 interrupt mask register (rd/wr) 0 0 0 0 0 00 a0 a1 a2 a3 a4 hex register description/accessibility address lines table 4. address mapping used to select the memory management scheme and enable interrupts for the current message. the read/write accessibility can be used as an aid for testing the sp?ace ii hybrid. time tag register: maintains the value of a real-time clock. the resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 s/lsb. the tag_clk input signal also may cause an external oscillator to clock the time tag register. start-of-message (som) and end-of-message (eom) sequences in bc, rt, and
8 data device corporation www.ddc-web.com bu-63825 c-02/06-0 end of message 0(lsb) bc status set/rt mode code/mt pattern trigger 1 format error 2 bc end of frame 3 bc/rt selected message 4 rt circular buffer rollover 5 time tag rollover 6 rt address parity error 7 bc retry 8 hs fail 9 mt data stack rollover 10 mt command stack rollover 11 bc/rt command stack rollover 12 bc/rt transmitter timeout 13 ram parity error 14 reserved 15(msb) description bit table 5. interrupt mask register (read/write 00h) message monitor modes cause a write of the current value of the time tag register to the stack area of ram. interrupt status register: mirrors the interrupt mask register and contains a master interrupt bit. it allows the host processor to determine the cause of an interrupt request by means of a single read operation. configuration registers #3, #4, and #5: used to enable many of the bu-63825?s advanced features. these include all the enhanced mode features; that is, all the functionality beyond that of the previous generation product, the bus-61559 advanced integrated mux hybrid with enhanced rt features (aim-hy?er). for bc mode, the enhanced mode fea- tures include the expanded bc control word and bc block status word, additional stop-on-error and stop-on-status set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, expanded status word masking, and the capability to generate interrupts following the completion of any selected message. for rt mode, the enhanced mode fea- tures include the expanded rt block status word, the combined rt/selective message monitor mode, internal wrapping of the r tf ail output signal (from the m-rad chip) to the r tfla g rt status word bit, the double buffering scheme for individual receive (broadcast) subaddresses, and the alternate (fully soft- ware programmable) rt status word. for mt mode, use of the enhanced mode enables use of the selective message monitor, the combined rt/selective monitor modes, and the monitor trig- gering capability. data stack address register: used to point to the current address location in shared ram used for storing message words (second command words, data words, rt status words) in the selective word monitor mode. frame time remaining register: provides a read only indication of the time remaining in the cur- rent bc frame. the resolution of this register is 100s/lsb. message time remaining register: provides a read only indication of the time remaining before the start of the next message in a bc frame. the resolution of this register is 1 s/lsb. bc frame/rt last command/mt trigger word register: in bc mode, it programs the bc frame time, for use in the frame auto-repeat mode. the resolution of this register is 100 s/lsb, with a range of 6.55 seconds; in rt mode, this register stores the current (or most previous) 1553 command word processed by the sp?ace ii rt; in the word monitor mode, this register speci- fies a 16-bit trigger (command) word. the trigger word may be used to start or stop the monitor, or to generate interrupts. status word register and bit word registers: provide read-only indications of the bu-63825?s rt status and bit words. test mode registers 0-7: these registers may be used to facilitate production or mainte- nance testing of the sp?ace ii and systems incorporating the sp?ace ii hybrid.
9 data device corporation www.ddc-web.com bu-63825 c-02/06-0 monitor active (read only) rt message in progress (read only) rt message in progress (read only) bc message in progress (read only) 0 (lsb) monitor triggered (read only) s00 not used bc frame in progress (read only) 1 monitor enabled (read only) s01 not used bc enabled (read only) 2 not used s02 not used doubled/single retry 3 not used s03 not used retry enabled 4 not used s04 not used intermessage gap timer enabled 5 not used s05 not used internal trigger enabled 6 external trigger enabled s06 r tfla g external trigger enabled 7 not used s07 subsystem fla g frame auto-repeat 8 stop-on-trigger s08 ser vice req uest status set stop-on-frame 9 start-on-trigger s09 b usy status set stop-on-message 10 trigger enabled word s10 d ynamic b us contr ol a ccept ance frame stop-on-error 11 message monitor enabled (mmt) message monitor enabled (mmt) message monitor enabled (mmt) message stop-on-error 12 current area b/a current area b/a current area b/a current area b/a 13 (logic 1) (logic 0) (logic 0) mt/bc-r t (logic 0) 14 (logic 0) (logic 1) (logic 1) rt/bc-mt (logic 0) 15 (msb) monitor function rt with alternate status rt without alternate status bc function (bits 11-0 enhanced mode only) bit table 6. configuration register #1 (read/write 01h) separate broadcast data 0(lsb) enhanced rt memory management 1 clear service request 2 level/pulse interrupt request 3 interrupt status auto clear 4 load time tag on synchronize 5 clear time tag on synchronize 6 time tag resolution 0 (ttr0) 7 time tag resolution 1 (ttr1) 8 time tag resolution 2 (ttr2) 9 256-word boundary disable 10 overwrite invalid data 11 rx sa double buffer enable 12 busy lookup table enable 13 logic ?0? 14 enhanced interrupts 15(msb) description bit table 7. configuration register #2 (read/write 02h) reset 0(lsb) bc/mt start 1 interrupt reset 2 time tag reset 3 time tag test clock 4 bc stop-on-frame 5 bc/mt stop-on-message 6 reserved 7 ? ? ? ? ? ? reserved 15(msb) description bit table 8. start/reset register (write 03h)
10 data device corporation www.ddc-web.com bu-63825 c-02/06-0 command stack pointer 0 0(lsb) ? ? ? ? ? ? command stack pointer 15 15(msb) description bit table 9. bc/rt command stack pointer reg. (read 03h) rt-rt format 0(lsb) broadcast format 1 mode code format 2 subsys flag bit mask 1553a/b select 3 eom interrupt enable 4 mask broadcast bit 5 off line self test 6 bus channel a/b 7 retry enabled 8 reserved bits mask 9 terminal flag bit mask 10 subsys busy bit mask 12 service request bit mask 13 m.e. mask 14 reserved 15(msb) description bit 11 table 10. bc control word register (read/write 04h) bcst: memory management 0 (mm0) 0(lsb) bcst: memory management 1 (mm1) 1 bcst: memory management 2 (mm2) 2 tx: memory management 1 (mm1) bcst: circ buf int 3 bcst: eom int 4 rx: memory management 0 (mm0) 5 rx: memory management 1 (mm1) 6 rx: memory management 2 (mm2) 7 rx: circ buf int 8 rx: eom int 9 tx: memory management 0 (mm0) 10 tx: memory management 2 (mm2) 12 tx: circ buf int 13 tx: eom int 14 rx: double buffer enable 15(msb) description bit 11 table 11. rt subaddress control word (read/write 04h) time tag 0 0(lsb) ? ? ? ? ? ? time tag 15 15(msb) description bit table 12. time tag register (read/write 05h) end of message 0(lsb) bc status set/rt mode code /mt pattern trigger 1 format error 2 mt command stack rollover bc end of frame 3 bc/rt selective message 4 rt circular buffer rollover 5 time tag rollover 6 rt address parity error 7 bc retry 8 hs fail 9 mt data stack rollover 10 bc/rt command stack rollover 12 bc/rt transmitter timeout 13 ram parity error 14 master interrupt 15(msb) description bit 11 table 13. interrupt status register (read 06h) enhanced mode code handling 0(lsb) 1553a mode codes enable 1 rtfail-flag wrap enable 2 mt command stack size 0 busy rx transfer disable 3 illegal rx transfer disable 4 alternate status word enable 5 override mode t/r error 6 illegalization disabled 7 mt data stack size 0 8 mt data stack size 1 9 mt data stack size 2 10 mt command stack size 1 12 bc/rt command stack size 0 13 bc/rt command stack size 1 14 enhanced mode enable 15(msb) description bit 11 table 14. configuration register #3 (read/write 07h)
11 data device corporation www.ddc-web.com bu-63825 c-02/06-0 test mode 0 0(lsb) test mode 1 1 test mode 2 2 broadcast mask enable/xor latch rt address with config #5 3 mt tag gap option 4 valid busy/no data 5 valid m.e./no data 6 2nd retry alt/same bus 7 1st retry alt/same bus 8 retry if status set 9 retry if -a and m.e. 10 expanded bc control word enable 12 mode command override busy 13 inhibit bit word if busy 14 external bit word enable 15(msb) description bit 11 table 15. configuration register #4 (read/write 08h) rt address parity 0(lsb) rt address 0 1 rt address 1 2 expanded crossing enabled rt address 2 3 rt address 3 4 rt address 4 5 rt address latch/transp arent (see note) 6 broadcast disabled 7 gap check enabled 8 response timeout select 0 9 response timeout select 1 10 external tx inhibit b, read only 12 external tx inhibit a, read only 13 single ended select 14 12mhz clock select 15(msb) description bit 11 table 16. configuration register #5 (read/write 09h) monitor data stack address 0 0(lsb) ? ? ? ? ? ? monitor data stack address 15 15(msb) description bit table 17. monitor data stack address register (read/write 0ah) note: read only, logic ?0? for 61582, logic ?1? for 61583. bc frame time remaining 0 0(lsb) ? ? ? ? ? ? bc frame time remaining 15 15(msb) description bit table 18. bc frame time remaining register (read/write 0bh) note: resolution 100 s per lsb note: resolution = 1 s per lsb bc message time remaining 0 0(lsb) ? ? ? ? ? ? bc message time remaining 15 15(msb) description bit table 19. bc message time remaining register (read/write 0ch) terminal flag 0(lsb) dynamic bus control accept 1 subsystem flag 2 logic ?0? busy 3 broadcast command received 4 reserved 5 reserved 6 reserved 7 service request 8 instrumentation 9 message error 10 logic ?0? 13 logic ?0? 14 logic ?0? 12 logic ?0? 15(msb) description bit 11 table 21. rt status word register (read/write 0eh) bit 0 0(lsb) ? ? ? ? ? ? bit 15 15(msb) description bit table 20. bc frame time/rt last command/ trigger register (read/write 0dh)
12 data device corporation www.ddc-web.com bu-63825 c-02/06-0 command word contents error 0(lsb) rt-rt 2nd command word error 1 rt-rt no response error 2 transmitter shutdown b rt-rt gap/sync/address error 3 parity/manchester error received 4 incorrect sync received 5 low word count 6 high word count 7 channel b/a 8 terminal flag inhibited 9 transmitter shutdown a 10 handshake failure 12 loop test failure a 13 loop test failure b 14 transmitter timeout 15(msb) description bit 11 table 22. rt bit word register (write 0fh) note: tables 23 to 26 are not registers, but they are words stored in ram. invalid word 0(lsb) incorrect sync type 1 word count error 2 status set wrong status address/no gap 3 good data block transfer 4 retry count 0 5 retry count 1 6 masked status set 7 loop test fail 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15(msb) description bit 11 table 23. bc mode block status word command word contents error 0(lsb) rt-rt 2nd command error 1 rt-rt gap/sync/address error 2 rt-rt format invalid word 3 incorrect sync 4 word count error 5 illegal command word 6 data stack rollover 7 loop test fail 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15(msb) description bit 11 table 24. rt mode block status word gap time mode code 0(lsb) contiguous data/gap 1 channel b/a 2 command/d a t a 3 error 4 br o adcast 5 this r t 6 word flag 7 ? ? ? ? ? ? gap time 15(msb) description bit 8 table 25. word monitor identification word command word contents error 0(lsb) rt-rt 2nd command error 1 rt-rt gap/sync/address error 2 rt-rt transfer invalid word 3 incorrect sync 4 word count error 5 reserved 6 data stack rollover 7 good data block transfer 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15(msb) description bit 11 table 26. message monitor mode block status word
13 data device corporation www.ddc-web.com bu-63825 c-02/06-0 bc controller (bc) architecture the bc protocol of the bu-63825 implements all mil-std- 1553b message formats. message format is programmable on a message-by-message basis by means of bits in the bc control word and the t/r bit of the command word for the respective message. the bc control word allows 1553 message format, 1553a/b type rt, bus channel, self-test, and status word mask- ing to be specified on an individual message basis. in addition, automatic retries and/or interrupt requests may be enabled or disabled for individual messages. the bc performs all error checking required by mil-std-1553b. this includes validation of response time, sync type and sync encoding, manchester ii encoding, parity, bit count, word count, status word rt address field, and various rt-to-rt transfer errors. the bu-63825?s bc response timeout value is programmable with choices of 18, 22, 50, and 130 s. the longer response timeout values allow for operation over long buses and/or the use of repeaters. figure 2 illustrates bc intermessage gap and frame timing. the bu-63825 may be programmed to process bc frames of up to 512 messages with no processor intervention. it is possible to program for either single frame or frame auto-repeat operation. in the auto-repeat mode, the frame repetition rate may be con- trolled either internally, using a programmable bc frame timer, or from an external trigger input. the internal bc frame time is pro- grammable up to 6.55 seconds in increments of 100 s. in addi- tion to bc frame time, intermessage gap time, defined as the start of the current message to the start of the subsequent mes- sage, is programmable on an individual message basis. the time between individual successive messages is programmable up to 65.5 ms, in increments of 1 s. bc memory organization table 27 illustrates a typical memory map for bc mode. it is important to note that the only fixed locations for the bu-63825 in the standard bc mode are for the two stack pointers (address locations 0100 (hex) and 0104) and for the two message count locations (0101 and 0105). enabling the frame auto-repeat mode will reserve four more memory locations for use in the enhanced bc mode; these locations are for the two initial stack pointers (address locations 102 (hex) and 106) and for the initial message no. 1 message no. 2 message no. 1 message gap time for message no. 1 bc frame time intermessage gap time figure 2. bc message gap and frame timing note: used only in the enhanced bc mode with frame auto-repeat enabled. stack b 3f00-3fff not used 3eee-3eff message block 416 3ec8-3eed ? ? ? ? initial message count a (see note) (auto-frame repeat mode) ? ? message block 2 0154-0179 message block 1 012e-0153 message block 0 0108-012d initial message count b (see note) (auto-frame repeat mode) 0107 initial stack pointer b (see note) (auto-frame repeat mode) 0106 message count b 0105 stack pointer b 0104 initial stack pointer a (see note) (auto-frame repeat mode) 0102 message count a (fixed location) 0101 stack pointer a (fixed location) 0100 stack a 0000-00ff description address (hex) 0103 table 27. typical bc memory organization (shown for 4k ram) message count locations (103 and 107). the user is free to locate the stack and bc message blocks anywhere else within the 64k (16k internal) shared ram address space. for simplicity of illustration, assume the allocation of the maxi- mum length of a bc message for each message block in the typ- ical bc memory map of table 27. the maximum size of a bc message block is 38 words, for an rt-to-rt transfer of 32 data words (control + 2 commands + loopback + 2 status words + 32 data words). note, however, that this example assumes the disabling of the 256-word boundaries.
14 data device corporation www.ddc-web.com bu-63825 c-02/06-0 bc memory management figure 3 illustrates the bu-63825?s bc memory management scheme. one of the bc memory management features is the global double buffering mechanism. this provides for two sets of the various bc mode data structures: stack pointer and message counter locations, descriptor stack areas, and bc message blocks. bit 13 of configuration register #1 selects the current active area. at any point in time, the bu-63825?s internal 1553 memory management logic may access only the various data structures within the ?active? area. figure 3 delineates the ?active? and ?inactive? areas by the nonshaded and shaded areas, respectively; however, at any point in time, both the ?active? and ?nonactive? areas are accessible by the host proces- sor. in most applications, the host processor will access the ?non- active? area, while the 1553 bus processes the ?active? area mes- sages. the bc may be programmed to transmit multimessage frames of up to 512 messages. the number of messages to be processed is programmable by the active area message count location in the shared ram, initialized by the host processor. in addition, the host processor must initialize another location, the active area stack pointer. the stack pointer references the four-word mes- sage block descriptor in the stack area of shared ram for each message to be processed. the bc stack size is programmable with choices of 256, 512, 1024, and 2048 words. in the bc frame auto-repeat mode, the initial stack pointer and initial message counter locations must be loaded by the host prior to the processing of the first frame. the single frame mode does not use these two locations the third and fourth words of the bc block descriptor are the intermessage gap time and the message block address for the respective message. these two memory locations must be writ- ten by the host processor prior to the start of message process- ing. use of the intermessage gap time is optional. the block address pointer specifies the starting location for each message block. the first word of each bc message block is the bc control word. at the start and end of each message, the block status and time tag words write to the message block descriptor in the stack. the block status word includes indications of message in process or message completion, bus channel, status set, response timeout, retry count, status address mismatch, loop test (on-line self-test) failure, and other error conditions. table 23 illustrates the bit mapping of the bc block status word. the 16-bit time tag word will reflect the current contents of the inter- nal time tag register. this read/writable register, which oper- ates for all three modes, has programmable resolution of from 2 to 64 s/lsb. in addition, the time tag register may be clocked from an external source. 15 13 0 current area b/a configuration register 1 initial stack pointers (note) initial message counters message counters stack pointers block status word time tag word message gap time word message block addr descriptor stacks message blocks message block message block figure 3. bc mode memory management
15 data device corporation www.ddc-web.com bu-63825 c-02/06-0 bc message block formats and bc control word in bc mode, the bu-63825 supports all mil-std-1553 message formats. for each 1553 message format, the bu-63825 man- dates a specific sequence of words within the bc message block. this includes locations for the control, command and (transmitted) data words that are to be read from ram by the bc-to-rt transfer control word receive command word data word #1 data word #2 . . . last data word last data word looped back status received last data word . . . data word #2 data word #1 status received transmit command looped back transmit command word control word rt-to-bc transfer transmit command looped back rx rt status word last data . . . data #2 data #1 tx rt status word transmit command receive command control word rt-to-rt transfer mode command looped back status received mode command control word mode code; no data mode command looped back data word status received tx mode command control word tx mode code; with data tx command looped back last data . . . data #2 data #1 tx rt status word tx command rx broadcast command control word rt-to-rts (broadcast) transfer last data status word last data . . . data #2 data #1 broadcast command control word broadcast data word data word looped back status received rx mode command control word rx mode code; with data broadcast mode command looped back broadcast mode command control word broadcast mode code; no data data word looped back data word broadcast mode command control word broadcast mode code; with data figure 4. bc message block formats bc protocol logic. in addition, subsequent contiguous locations must be allocated for storage of received loopback, rt status and data words. figure 4 illustrates the organization of the bc message blocks for the various mil-std-1553 message for- mats. note that for all of the message formats, the bc control word is located in the first location of the message block. the bc control word is not transmitted on the 1553 bus. instead, it contains bits that select the active bus and message format, enable off-line self-test, masking of status word bits, enable retries and interrupts, and specify mil-std-1553a or - 1553b error handling. the bit mapping and definitions of the bc control word are illustrated in table 10. the bc control word is followed by the command word to be transmitted, and subsequently by a second command word (for an rt-to-rt transfer), followed by data words to be transmitted (for receive commands). the location after the last word to be transmitted is reserved for the loopback word. the loopback word is an on-line self-test feature. the subsequent locations after the loopback word are reserved for received status words and data words (for transmit commands). automatic retries the bu-63825 bc implements automatic message retries. when enabled, retries will occur, following response timeout or format error conditions. as additional options, retries may be enabled when the message error status word bit is set by a 1553a rt or following a ?status set? condition. for a failed message, either one or two message retries will occur, and the bus channel (same or alternate) is independently programmable for the first and second retry attempts. retries may be enabled or disabled on an individual message basis. bc interrupts bc interrupts may be enabled by the interrupt mask register for stack rollover, retry, end-of-message (global), end-of- message (in conjunction with the bc control word for individual messages), response timeout, message error, end of bc frame, and status set conditions. the definition of ?status set? is pro- grammable on an individual message basis by means of the bc control word. this allows for masking (?care/don?t care?) for the individual rt status word bits. remote terminal (rt) architecture the rt protocol design of the bu-63825 represents ddc?s fifth generation implementation of a 1553 rt. one of the salient fea- tures of the sp?ace ii?s rt architecture is its true multiprotocol functionality. this includes programmable options for support of mil-std-1553a, the various mcair protocols, and mil-std- 1553b notice 2. the bu-63825 rt response time is 2 to 5 s dead time (4 to 7 s per 1553b), providing compliance to all the 1553 protocols. additional multiprotocol features of the bu-
16 data device corporation www.ddc-web.com bu-63825 c-02/06-0 63825 include options for full software control of rt status and built-in-test (bit) words. alternatively, for 1553b applications, these words may be formulated in real time by the bu-63825 protocol logic. the bu-63825 rt protocol design implements all the mil-std- 1553b message formats and dual redundant mode codes. this design is based largely on previous generation products that have passed seafac testing for mil-std-1553b compliance. the sp?ace ii rt performs comprehensive error checking, word and format validation, and checks for various rt-to-rt transfer errors. other key features of the bu-63825 rt include a set of interrupt conditions, internal command illegalization, and pro- grammable busy by subaddress. rt memory organization table 28 illustrates a typical memory map for the sp?ace ii in rt mode. as in bc mode, the two stack pointers reside in fixed locations in the shared ram address space: address 0100 (hex) for the area a stack pointer and address 0104 for the area b stack pointer. besides the stack pointer, for rt mode there are several other areas of the bu-63825 address space designated as fixed locations. all rt modes of operation require the area a and area b lookup tables. also allocated, are several fixed loca- tions for optional features: command illegalization lookup table, mode code selective interrupt table, mode code data table, and busy bit lookup table. it should be noted that any unen- abled optional fixed locations may be used for general purpose storage (data blocks). the rt lookup tables, which provide a mechanism for mapping data blocks for individual tx/rx/bcst-subaddresses to areas in the ram, occupy address range locations 0140 to 01bf for area a and 01c0 to 023f for area b. the rt lookup tables include subaddress control words and the individual data block pointers. if used, address range 0300-03ff will be dedicated as the illegalizing section of ram. the actual stack ram area and the individual data blocks may be located in any of the nonfixed areas in the shared ram address space. rt memory management another salient feature of the sp?ace ii series products is the flex- ibility of its rt memory management architecture. the rt archi- tecture allows the memory management scheme for each transmit, receive, or broadcast subaddress to be programmable on a sub- address basis. also, in compliance with mil-std-1553b notice 2, the bu-63825 provides an option to separate data received from broadcast messages from nonbroadcast received data. besides supporting a global double buffering scheme (as in bc mode), the sp?ace ii rt provides a pair of 128-word lookup tables for memory management control, programmable on a subaddress basis (refer to table 29). the 128-word tables include 32-word tables for transmit message pointers and receive message pointers. there is also a third, optional lookup data block 476 3fe0-3fff ? ? ? ? ? ? data block 6 0420-043f data block 5 0400-041f command illegalizing table (fixed area) 0300-03ff reserved data block 1-4 0280-02ff data block 0 0260-027f (not used) 0248-025f busy bit lookup table (fixed area) 0240-0247 lookup table b (fixed area) 01c0-023f lookup table a (fixed area) 0140-01bf mode code data (fixed area) 0110-013f mode code selective interrupt table (fixed area) 0108-010f stack pointer b (fixed location) 0104 reserved 0101-0103 stack pointer a (fixed location) 0100 stack a 0000-00ff description address (hex) 0105-0107 table 28. typical rt memory map (shown for 16k ram) table for broadcast message pointers, providing notice 2 com- pliance, if necessary. the fourth section of each of the rt lookup tables stores the 32 subaddress control words (refer to table 11 and table 30). the individual subaddress control words may be used to select the rt memory management option and interrupt scheme for each transmit, receive, and (optionally) broadcast subaddress. subaddress control word lookup table (optional) sacw_sa0 . . . sacw_sa31 0220 . . . 023f 01a0 . . . 01bf broadcast lookup table optional bcst_sa0 . . . bcst_sa31 0200 . . . 021f 0180 . . . 019f transmit lookup table tx_sa0 . . . tx_sa31 01e0 . . . 01ff 0160 . . . 017f receive (/broadcast) lookup table rx(/bcst)_sa0 . . . rx(/bcst)_sa31 01c0 . . . 01df 0140 . . . 015f comment description area b area a table 29. look-up tables
17 data device corporation www.ddc-web.com bu-63825 c-02/06-0 for each transmit subaddress, there are two possible memory management schemes: (1) single message; and (2) circular buffer. for each receive (and optionally broadcast) subaddress, there are three possible memory management schemes: (1) sin- gle message; (2) double buffered; and (3) circular buffer. for each transmit, receive and broadcast subaddress, there are two interrupt conditions programmable by the respective subaddress control word: (1) after every message to the sub- address; (2) after a circular buffer rollover. an additional table in ram may be used to enable interrupts following selected mode code messages. when using the circular buffer scheme for a given subaddress, the size of the circular buffer is programmable by three bits of the subaddress control word (see table 30). the options for cir- cular buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192 data words. circular buffer of specified size 8192-word 1 1 1 4096-word 0 1 1 1024-word 0 0 1 512-word 1 1 0 256-word 0 1 0 128-word 1 0 0 single message or double buffered 0 0 0 comment description mm0 mm1 mm2 table 30. subaddress control word memory management subaddress buffer scheme 2048-word 1 0 1 data blocks data block data block block status word time tag word data block pointer received command word descriptor stacks look-up table addr look-up table (data block addr) 15 13 0 current area b/a configuration register stack pointers (see note) note: lookup table is not used for mode commands when enhanced mode codes are enabled. figure 5. rt memory management: single message mode single message mode figure 5 illustrates the rt single message memory manage- ment scheme. when operating the bu-63825 in its ?aim-hy? (default) mode, the single message scheme is implemented for all transmit, receive, and broadcast subaddresses. in the single message mode (also in the double buffer and circular buffer modes), there is a global double buffering scheme, controlled by bit 13 of configuration register #1. this selects from between the two sets of the various data structures shown in the figure: the stack pointers (fixed addresses), descriptor stacks (user defined addresses), rt lookup tables (fixed addresses), and rt data word blocks (user defined addresses). figures 5, 6, and 7 delineate the ?active? and ?nonactive? areas by the non- shaded and shaded areas, respectively. as shown, the sp?ace ii stores the command word from each message received, in the fourth location within the message descriptor (in the stack) for the respective message. the t/r bit, subaddress field, and (optionally) broadcast/own address, index into the active area lookup table, to locate the data block pointer for the current message. the bu-63825 rt memory management logic then accesses the data block pointer to locate the starting address for the data word block for the cur- rent message. the maximum size for an rt data word block is 32 words. for a particular subaddress in the single message mode, there is overwriting of the contents of the data blocks for receive/broad- cast subaddresses ? or overreading, for transmit subaddresses. in the single message mode, it is possible to access multiple data blocks for the same subaddress. this, however, requires the intervention of the host processor to update the respective lookup table pointer. to implement a data wraparound subad- dress, as required by notice 2 of mil-std-1553b, the single message scheme should be used for the wraparound subad- dress. notice 2 recommends subaddress 30 as the wraparound subaddress.
18 data device corporation www.ddc-web.com bu-63825 c-02/06-0 circular buffer mode figure 6 illustrates the rt circular buffer memory manage- ment scheme. the circular buffer mode facilitates bulk data transfers. the size of the rt circular buffer, shown on the right side of the figure, is programmable from 128 to 8192 words (in even powers of 2) by the respective subaddress control word. as in the single message mode, the host processor initially loads the individual lookup table entries. at the start of each message, the sp?ace ii stores the lookup table entry in the third position of the respective message block descriptor in the stack area of ram, as in the single message mode. the sp?ace ii transfers receive or transmit data words to (from) the circular buffer, starting at the location referenced by the lookup table pointer. at the end of a valid (or, optionally, invalid) message, the value of the lookup table entry updates to the next location after the last address accessed for the current message. as a result, data words for the next message directed to the same tx/rx(/bcst) subaddress will be accessed from the next contiguous block of address locations within the circular buffer. as a recommended option, the lookup table pointers may be programmed to not update following an invalid receive (or broadcast) message. this allows the 1553 bus controller to retry the failed message, result- ing in the valid (retried) data overwriting the invalid data. this eliminates overhead for the rt?s host processor. when the point- er reaches the lower boundary of the circular buffer (located at 128, 256, . . . 8192-word boundaries in the bu-63825 address space), the pointer moves to the top boundary of the circular buffer, as figure 6 shows. implementing bulk data transfers the use of the circular buffer scheme is ideal for bulk data trans- fers; that is, multiple messages to/from the same subaddress. the recommendation for such applications is to enable the cir- cular buffer interrupt request. by so doing, the routine transfer of multiple messages to the selected subaddress, including errors and retries, is transparent to the rt?s host processor. by strate- gically initializing the subaddress?s lookup table pointer prior to the start of the bulk transfer, the bu-63825 may be configured to issue an interrupt request only after it has received the anticipat- ed number of valid data words to the designated subaddress. subaddress double buffering mode for receive (and broadcast) subaddresses, the bu-63825 rt offers a third memory management option, subaddress double buffering. subaddress double buffering provides a means of ensuring data consistency. figure 7 illustrates the rt subaddress double buffering scheme. like the single message and circular buffer modes, the double buffering mode may be selected on a subaddress basis by means of the subaddress control word. the purpose of the double buffering mode is to provide the host processor a convenient means of accessing the most recent, valid data received to a given subaddress. this serves to ensure the highest possible degree of data consisten- cy by allocating two 32-bit data word blocks for each individual receive (and/or broadcast) subaddress. at a given point in time, one of the two blocks will be designated as the ?active? 1553 data block while the other will be designat- ed as the ?inactive? block. the data words from the next receive message to that subaddress will be stored in the ?active? block. 15 13 0 received (transmitted) message data (next location) pointer to current data block pointer to next data block look-up table entry look-up tables look-up table address block status word time tag word data block pointer received command word configuration register #1 stack pointers descriptor stack current area b/a 1. tx/rx/bcst_sa look-up table entry is updated following valid receive (broadcast) message or following completion of transit message notes: * 100% circular buffer rollover interrupt circular data buffer* (128,256,...8192 words) figure 6. rt memory management: circular buffer mode
19 data device corporation www.ddc-web.com bu-63825 c-02/06-0 upon completion of the message, provided that the message was valid and subaddress double buffering is enabled, the bu- 63825 will automatically switch the ?active? and ?inactive? blocks for the respective subaddress. the sp?ace ii accomplishes this by toggling bit 5 of the subaddress?s lookup table pointer and rewriting the pointer. as a result, the most recent valid block of received data words will always be readily accessible to the host processor. as a means of ensuring data consistency, the host processor is able to reliably access the most recent valid, received data word block by performing the following sequence: (1) disable the double buffering for the respective subaddress by the subaddress control word. that is, temporarily switch the subaddress?s memory management scheme to the single message mode. (2) read the current value of the receive (or broadcast) subad- dress?s lookup table pointer. this points to the current ?active? data word block. by inverting bit 5 of this pointer value, it is pos- sible to locate the start of the ?inactive? data word block. this block will contain the data words received during the most recent valid message to the subaddress. (3) read out the words from the ?inactive? (most recent) data word block. (4) re-enable the double buffering mode for the respective sub- address by the subaddress control word. rt interrupts as in bc mode, the bu-63825 rt provides many maskable interrupts. rt interrupt conditions include end of (every) message, message error, selected subaddress (subaddress control word) interrupt, circular buffer rollover, selected mode code interrupt, and stack rollover. descriptor stack at the beginning and end of each message, the bu-63825 rt stores a four-word message descriptor in the active area stack. the rt stack size is programmable, with choices of 256, 512, 1024, and 2048 words. figures 5, 6, and 7 show the four words: block status word, time tag word, data block pointer, and the 1553 received command word. the rt block status word includes indications of message in-progress or message complete, bus channel, rt-to-rt transfer and rt-to-rt transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, and other error conditions. table 24 shows the bit mapping of the rt block status word. as in bc mode, the time tag word stores the current contents of the bu-63825?s read/writable time tag register. the resolu- tion of the time tag register is programmable from among 2, 4, 8, 16, 32, and 64 s/lsb. also, incrementing of the time tag counter may be from an external clock source or via software command. the sp?ace ii stores the contents of the accessed lookup table location for the current message, indicating the starting location of the data word block, as the data block pointer. this serves as a convenience in locating stored message data blocks. the figure 7. rt memory management: subaddress double buffering mode 15 13 0 block status word time tag word data block pointer received command word configuration register stack pointers descriptor stack current area b/a data blocks data block 1 data block 0 x..x 0 yyyyy x..x 1 yyyyy receive double buffer enable subaddress control word msb data block pointer look-up tables #1
20 data device corporation www.ddc-web.com bu-63825 c-02/06-0 sp?ace ii stores the full 16-bit 1553 command word in the fourth location of the rt message descriptor. rt command illegalization the bu-63825 provides an internal mechanism for rt com- mand illegalization. in addition, there is a means for allowing the setting of the busy status word bit to be only for a programmed subset of the transmit/receive/broadcast subaddresses. the illegalization scheme uses a 256-word area in the bu- 63825?s address space. a benefit of this feature is the reduction of printed circuit board requirements, by eliminating the need for an external prom, pld, or ram device that does the illegaliz- ing function. the bu-63825?s illegalization scheme provides maximum flexibility, allowing any subset of the 4096 possible combinations of broadcast/own address, t/r bit, subaddress, and word count/mode code to be illegalized. another advantage of the ram-based illegalization technique is that it provides for a high degree of self-testability. addressing the illegalization table table 31 illustrates the addressing scheme of the illegalization ram. as shown, the base address of the illegalizing ram is 0300 (hex). the sp?ace ii formulates the index into the illegalizing table based on the values of br o adcast /ownaddress address, t/r bit, subaddress, and the msb of the word count/mode code field (wc/mc4) of the current command word. the internal ram has 256 words reserved for command illegal- ization. broadcast commands may be illegalized separately from nonbroadcast receive commands and mode commands. commands may be illegalized down to the word count level. for example, a one-word receive command to subaddress 1 may be legal, while a two-word receive command to subaddress 1 may be illegalized. the first 64 words of the illegalization table refer to broadcast receive commands (two words per subaddress). the next 64 words refer to broadcast transmit commands. since nonmode code broadcast transmit commands are by definition invalid, this section of the table (except for subaddresses 0 and 31) does not need to be initialized by the user. the next 64 words correspond to nonbroadcast receive commands. the final 64 words refer to nonbroadcast transmit commands. messages with word count/ mode code (wc/mc) fields between 0 and 15 may be illegalized by setting the corresponding data bits for the respective even- numbered address locations in the illegalization table. likewise, messages with wc/mc fields between 16 and 31 may be illegal- ized by setting the corresponding data bits for the respective odd- numbered address locations in the illegalization table. the following should be noted with regards to command illegalization: (1) to illegalize a particular word count for a given broadcast/own address-t/r subaddress, the appropriate bit position in the respective illegalization word should be set to logic 1. a bit value of logic 0 designates the respective command word as a legal command. the bu-63825 will respond to an illegalized non- broadcast command with the message error bit set in its rt status word. (2) for subaddresses 00001 through 11110, the ?wc/mc? field specifies the word count field of the respective command word. for subaddresses 00000 and 11111, the ?wc/mc? field speci- fies the mode code field of the respective command word. (3) since nonmode code broadcast transmit messages are not defined by mil-std-1553b, the sixty (60) words in the illegal- ization ram, addresses 0342 through 037d, corresponding to these commands do not need to be initialized. the bu-63825 will not respond to a nonmode code broadcast transmit command, but will automatically set the message error bit in its internal status register, regardless of whether or not the corresponding bit in the illegalization ram has been set. if the next message is a transmit status or transmit last command mode code, the bu-63825 will respond with its message error bit set. wc4/mc4 0(lsb) sa0 1 sa1 2 0 sa2 3 sa3 4 sa4 5 t/r 6 br o adcast /own_address 7 1 8 1 9 0 10 0 12 0 13 0 14 0 15(msb) description bit 11 table 31. illegalization ram address definition
21 data device corporation www.ddc-web.com bu-63825 c-02/06-0 programmable busy as a means of providing compliance with notice 2 of mil-std- 1553b, the bu-63825 rt provides a software controllable means for setting the busy status word bit as a function of sub- address. by a busy lookup table in the bu-63825 address space, it is possible to set the busy bit based on command broadcast/own address, t/r bit, and subaddress. another pro- grammable option allows received data words to be either stored or not stored for messages when the busy bit is set. other rt functions the bu-63825 allows the hardwired rt address to be read by the host processor. also, there are options for the rt flag status word bit to be set under software control and/or automat- ically following a failure of the loopback self-test. other software controllable rt options include software programmable rt status and rt bit words, automatic clearing of the service request status word bit following a transmit vector word mode command, capabilities to clear and/or load the time tag register following receipt of synchronize mode commands, options regarding data word transfers for the busy and/or message error (illegal) status word bits, and for handling of 1553a and reserved mode codes. monitor (mt) architecture the bu-63825 provides three bus monitor (mt) modes: (1) the ?aim-hy? (default) or ?aim-hy?er? word monitor mode. (2) a selective message monitor mode. (3) a simultaneous remote terminal/selective message monitor mode. the strong recommendation for new applications is the use of the selective message monitor, rather than the word monitor. besides providing monitor filtering based on rt address,t/r bit, and subaddress, the message monitor eliminates the need to determine the start and end of messages by software. the devel- opment of such software tends to be a tedious task. moreover, at run time, it tends to entail a high degree of cpu overhead. word monitor in the word monitor mode, the bu-63825 monitors both 1553 buses. after initializing the word monitor and putting it on-line the bu-63825 stores all command, status, and data words received from both buses. for each word received from either bus, the bu-63825 stores a pair of words in ram. the first word is the 16 bits of data from the received word. the second word is the monitor identification (id), or ?tag? word. the id word con- tains information relating to bus channel, sync type, word validi- ty, and interword time gaps. the bu-63825 stores data and id words in a circular buffer in the shared ram address space. table 25 shows the bit mapping for the monitor id word. monitor trigger word there is a trigger word register that provides additional flexi- bility for the word monitor mode. the bu-63825 stores the value of the 16-bit trigger word in the mt trigger word register. the contents of this register represent the value of the trigger command word. the bu-63825 has programmable options to start or stop the word monitor, and/or to issue an interrupt request following receipt of the trigger command word from the 1553 bus. selective message monitor mode the bu-63825 selective message monitor provides features to greatly reduce the software and processing burden of the host cpu. the selective message monitor implements selective mon- itoring of messages from a dual 1553 bus, with the monitor fil- tering based on the rt address, t/r bit, and subaddress fields of received 1553 command words. the selective message monitor mode greatly simplifies the host processor software by distinguishing between command and status words. the selective message monitor maintains two stacks in the bu-63825 ram: a command stack and a data stack. simultaneous rt/message monitor mode the selective message monitor may function as a purely passive monitor or may be programmed to function as a simultaneous rt/monitor. the rt/monitor mode provides complete remote terminal (rt) operation for the bu-63825?s strapped rt address and bus monitor capability for the other 30 non-broadcast rt addresses. this allows the bu-63825 to simultaneously operate as a full function rt and ?snoop? on all or a subset of the bus activity involving the other rts on a bus. this type of operation is sometimes needed to implement a backup bus controller. the combined rt/selective monitor maintains three stack areas in the bu-63825 address space: an rt command stack, a monitor command stack, and a monitor data stack. the pointers for the various stacks have fixed locations in the bu-63825 address space. selective message monitor memory organization table 32 illustrates a typical memory map for the sp?ace ii in the selective message monitor mode. this mode of operation defines several fixed locations in the ram. these locations allo- cate in a manner that is compatible with the combined rt/selective message monitor mode. the fixed memory map consists of two monitor command stack pointers (location 102h and 106h), two monitor data stack pointers (locations 103h and 107h), and a selective message monitor lookup table (0280- 02ffh) based on rt address t/r , and subaddress. assume a monitor command stack size of 1k words, and a monitor data stack size of 4k words.
22 data device corporation www.ddc-web.com bu-63825 c-02/06-0 monitor command stack pointer b (fixed location) monitor command stack b (1k words) 0800-3fff not used (4k words) monitor command stack a (1k words) 3000-3fff 0400-07ff monitor data stack b (4k words) not used 2000-2fff 0300-03ff monitor data stack a (4k words) selective monitor lookup table (fixed area) 1000-1fff 0280-02ff not used (1k words) not used 0c00-0fff- 0108-027f monitor data stack pointer b (fixed location) 0107 not used 0104-0105 monitor data stack pointer a (fixed location) 0103 monitor command stack pointer a (fixed location) 0102 not used 0000-0101 description address (hex) 0106 table 32. typical selective message monitor memory map (shown for 16k ram) refer to figure 8 for an illustration of the selective message monitor operation. upon receipt of a valid command word, the bu-63825 will reference the selective monitor lookup table (a fixed block of addresses) to check for the condition (disabled/enabled) of the current command. if disabled, the bu- 63825 will ignore (and not store) the current message; if enabled, the bu-63825 will create an entry in the monitor command stack at the address location referenced by the monitor command stack pointer. similar to rt mode, the sp?ace ii stores a block status word, 16-bit time tag word, and data block pointer in the message descriptor, along with the received 1553 command word follow- ing reception of the command word. the sp?ace ii writes the block status and time tag words at both the start and end of the message. the monitor block status word contains indications of message in-progress or message complete, bus channel, monitor data stack rollover, rt-to-rt transfer and rt-to-rt transfer errors, message format error, and other error conditions. table 26 shows the message monitor block status word. the data block pointer references the first word stored in the monitor data stack (the first word following the command word) for the current message. the bu-63825 will then proceed to store the subsequent words from the message [possible second command word, data word(s), status word(s)] into consecutive locations in the monitor data stack. the size of the monitor command stack is programmable to 256, 1k, 4k, or 16k words. the monitor data stack size is pro- grammable to 512, 1k, 2k, 4k, 8k, 16k, 32k, or 64k words. monitor interrupts may be enabled for monitor command stack rollover, monitor data stack rollover, and/or end-of-message conditions. in addition, in the word monitor mode there may be an interrupt enabled for a monitor trigger condition. 15 13 0 block status word time tag word data block pointer received command word configuration register #1 monitor command stack pointers monitor command stacks current area b/a monitor data stacks monitor data block #n + 1 monitor data block #n current command word monitor data stack pointers if this bit is "0" (not selected) no words are stored in either the command stack or data stack. in addition, the command and data stack pointers will not be updated. note selective monitor lookup tables selective monitor enable (see note) offset based on rta4-rta0, t/r, sa4 monitor data stack 100% rollover interrupt monitor command stack 100% rollover interrupt figure 8. selective message monitor operation
23 data device corporation www.ddc-web.com bu-63825 c-02/06-0 processor and memory interface the sp?ace ii terminals provide much flexibility for interfacing to a host processor and optional external memory. figure 1 shows that there are 14 control signals, 6 of which are dual pur- pose, for the processor/memory interface. figures 9 through 14 illustrate six of the configurations that may be used for inter- facing the bu-63825 to a host processor bus. the various possi- ble configurations serve to reduce to an absolute minimum the amount of glue logic required to interface to 8-, 16-, and 32-bit processor buses. also included are features to facilitate interfac- ing to processors that do not have a ?wait state? type of hand- shake acknowledgment. finally, the sp?ace ii supports a reliable interface to an external dual port ram. this type of interface min- imizes the portion of the available processor bandwidth required to access the 1553 ram. the 16-bit buffered mode (figure 9) is the most common con- figuration used. it provides a direct, shared ram interface to a 16-bit or 32-bit microprocessor. in this mode, the sp?ace ii?s internal address and data buffers provide the necessary isolation between the host processor?s address and data buses and the corresponding internal memory buses. in the buffered mode, the 1553 shared ram address space limit is the bu-63825?s 16k words of internal ram. the 16-bit buffered mode provides a pair of pin-programmable options: (1) the logic sense of the rd/wr control input is selectable by the polarity_sel input; for example, write when rd/wr is low for motorola 680x0 processors; write when rd/wr is high for the intel i960 series microprocessors. (2) by strapping the input signal zer o w ait to logic ?1?, the sp?ace ii terminals may interface to processors that have an acknowledge type of handshake input to accommodate hard- ware controlled wait states; most current processor chips have such an input. in this case, the bu-63825 will assert its read y output low only after it has latched write data internally or has presented read data on d15-d0. by strapping zer o w ait to logic ?0?, it is possible to easily inter- face the bu-63825 to processors that do not have an acknowl- edge type of handshake input. an example of such a processor is analog device?s adsp2101 dsp chip. in this configuration, the processor can clear its strobe output before the completion of access to the bu-63825 internal ram or register. in this case, read y goes high following the rising edge of strbd and will stay high until completion of the transfer. read y will normally be low when zer o w ait is low. similar to the 16-bit buffered mode, the 16-bit transparent mode (figure 10) supports a shared ram interface to a host cpu. the transparent mode offers the advantage of allowing the buffer ram size to be expanded to up to 64k words, using external ram. a disadvantage of the transparent mode is that it requires external address and data buffers to isolate the processor buses from the memory/bu-63825 buses. a modified version of the transparent mode involves the use of dual port ram, rather than conventional static ram. refer to figure 11. this allows the host to access ram very quickly, the only limitation being the access time of the dual port ram. this configuration eliminates the bu-63825 arbitration delays for memory accesses. the worst case delay time occurs only during a simultaneous access by the host and the bu-63825 1553 logic to the same memory address. in general, this will occur very rarely and the sp?ace ii limits the delay to approximately 250 ns. figure 12 illustrates the connections for the 16-bit direct memory access (dma) mode. in this configuration the host processor, rather than the sp?ace ii terminal, arbitrates the use of the address and data buses. the arbitration involves the two dma output signals request (dtreq) , acknowledge (dt a ck) , and the input signal grant (dtgr t) . the dma interface allows the sp?ace ii components to interface to large amounts of sys- tem ram while eliminating the need for external buffers. for sys- tem address spaces larger than 64k words, it is necessary for the host processor to provide a page register for the upper address bits (above a15) when the bu-63825 accesses the ram (while asserting (dt a ck) low). the internal ram is accessible through the standard sp?ace ii interface (select , strbd , read yd , etc). the host cpu may access external ram by the sp?ace ii?s arbitration logic and out- put control signals, as illustrated in figure 12. alternatively, control of the ram may be shared by both the host processor and the sp?ace ii, as illustrated in figure 13. the latter requires the use of external logic, but allows the processor to access the ram directly at the full access speed of the ram, rather than waiting for the sp?ace ii handshake acknowledge output read y . figure 14 illustrates the 8-bit buffered mode. this interface allows a direct connection to 8-bit microprocessors and 8-bit microcontrollers. as in the 16-bit buffered configuration, the buffer ram limit is the bu-63825?s 16k words of internal ram. in the 8-bit mode, the host cpu accesses the bu-63825?s inter- nal registers and ram by a pair of 8-bit registers embedded in the sp?ace ii interface. the 8-bit interface may be further con- figured by three strappable inputs: zer o w ait , polarity_sel, and trigger_sel. by connecting zer o w ait to logic ?0?, the bu-63825 may be interfaced with minimal ?glue? logic to 8-bit microcontrollers, such as the intel 8051 series, that do not have an acknowledge type of hand- shake input. the programmable inputs polarity_sel and trigger_sel allow the bu-63825 to accommodate the differ- ent byte ordering conventions and ?a0? logic sense utilized by dif- ferent 8-bit processor families.
24 data device corporation www.ddc-web.com bu-63825 c-02/06-0 processor interface timing figures 16 and 17 illustrate the timing for the host processor to access the sp?ace ii?s internal ram or registers in the 16-bit, nonzero wait buffered mode. figure 16 illustrates the 16-bit, buffered, nonzero wait state mode read cycle timing while figure 17 shows the 16-bit, buffered, nonzero wait state mode write cycle timing. during a cpu transfer cycle, the signals strb and select must be sampled low on the rising edge of the system clock to request access to the bu-63825?s internal shared ram. the transfer will begin on the second rising system clock edge when strbd is low, provided select is sampled low and the 1553 protocol/memory management unit is not accessing the internal ram. the falling edge of the output signal ioen indicates the start of the transfer. the sp?ace ii latches the signals mem/reg and rd/wr internally on the first falling clock edge after the start of the transfer cycle. the address inputs latch internally on the first rising clock edge after the signal ioen goes low. note that the address lines may be latched at any time using the addr_lat input signal. the output signal read yd will be asserted low on the third (or 7th if it?s an internal read) rising system clock edge after ioen goes low. the assertion of read yd low indicates to the host processor that read data is available on the parallel data bus, or that write data has been stored. at this time, the cpu should bring the signal strbd high, completing the transfer cycle. address latch timing figure 15 illustrates the operation and timing of the address input latches for the buffered interface mode. in the transparent mode, the address buffers are always transparent. since the transparent mode requires the use of external buffers, external address latches would be required to demultiplex a multiplexed address bus. in the buffered mode however, the sp?ace ii?s inter- nal address latches may be used to perform the demultiplexing function. the addr_lat input signal controls address latch operation. when addr_lat is high, the outputs of the latch (which drive the sp?ace ii?s internal memory bus) track the state of address inputs a15 - a00. when low, the internal memory bus remains latched at the state of a15 - a00 just prior to the falling edge of addr_lat. miscellaneous self-test the bu-63825 products incorporate several self-test features. these features include an on-line wraparound self-test for all messages in bc and rt modes, an off-line wraparound self-test for bc mode, and several other internal self-test features. the bc/rt on-line loop test involves a wraparound test of the encoder/decoder and transceiver. the bc off-line self-test involves the encoder/decoder, but not the transceiver. these tests entail checking the received version of every transmitted word for validity (sync, encoding, bit count, parity) and checking the received version of the last transmitted word for a bit-by-bit comparison with the encoded word. the loopback test also fails if there is a timeout of the internal transmitter watchdog timer. a failure of the loop test results in setting a bit in the message?s block status word and, if enabled, will result in an interrupt request. with appropriate host processor software, the bc off- line test is able to exercise the parallel and serial data paths, encoder, decoder, and a substantial portion of the bc protocol and memory management logic. there are additional built-in self-test features, involving the use of three configuration register bits and the eight test registers. this allows a comprehensive test of the m-rad chip?s internal logic. these tests include an encoder test, a decoder test, a reg- ister test, a protocol test, and a test of the fail-safe (transmitter timeout) timer. in the test mode, the host processor can emulate arbitrary activ- ity on the 1553 buses by writing to a pair of test registers. the test mode can be operated in conjunction with the word monitor mode to facilitate end-to-end self-tests.
25 data device corporation www.ddc-web.com bu-63825 c-02/06-0 host sp'ace ii 55 ? 55 ? 8 7 5 4 1 2 3 ch. a tx/rxa tx/rxa 55 ? 55 ? 8 7 5 4 1 2 3 ch. b tx/rxb tx/rxb rtad4-rtad0 rt address, parity rtadp d15-d0 +5v -12v/-15v clk in 16 mhz clock oscillator zero_wait (note 2) address decoder select mem/reg rd/wr strbd readyd tag_clk rd/wr cpu strobe cpu acknowledge (note 4) reset notes: +5v mstclr ssflag/ext_trig int cpu interrupt request 3. zero wait should be strapped to logic "1" for non-zero wait interface and to logic "0" for zero wait interface. 4. cpu acknowledge processor input only for non-zero wait type of interface. 1. cpu address latch signal provided by processors with multiplexed address/data buses. 2. if polarity_sel = "1", then rd/wr is high to read. low to write. if polarity_sel = "0", then rd/wr is low to read. high to write. a15-a14 a13-a0 n/c addr_lat cpu address latch transparent/buffered +5v (note 1) polarity_sel (note 3) +5v 16/8_bit n/c n/c trigger_sel msb/lsb figure 9. 16-bit buffered mode
26 data device corporation www.ddc-web.com bu-63825 c-02/06-0 host sp'ace ii 55 ? 55 ? 8 7 5 4 1 2 3 ch. a tx/rxa tx/rxa 55 ? 55 ? 8 7 5 4 1 2 3 ch. b tx/rxb tx/rxb rtad4-rtad0 rt address, parity rtadp d15-d0 +5v -12v/-15v clk in 16 mhz clock oscillator rd/wr strbd readyd tag_clk cpu strobe cpu acknowledge reset +5v mstclr ssflag/ext_trig int cpu interrupt request '245 dir en cpu d15-d0 ram 64k x 16 max wr oe cs memwr memoe ioen dtreq dtgrt '244 en address decoder en address decoder memena-in a15-a0 cpu a15-a0 memena-out select mem/reg transparent/buffered +5v figure 10. 16-bit transparent mode
27 data device corporation www.ddc-web.com bu-63825 c-02/06-0 host sp'ace ii dual port ram cs-l wr-l oe-l cs-r wr-r oe-r memena-out memwr memoe busy-l busy-r n/c cpu d15-d0 cpu address dir '245 en '244 en d15-d0 a15-a0 cpu a4-a0 a4-a0 rd/wr rd/wr address decoder 1553 ram select 1553 reg select mem/reg ioen dtreq dtgrt dtack n/c select strbd cpu data strobe transparent/buffered +5v int cpu interrupt request readyd reset +5v mstclr cpu ready memena-in +5v 16 mhz clock oscillator -12v/-15v +5v clk in figure 11. 16-bit transparent mode using dual port ram
28 data device corporation www.ddc-web.com bu-63825 c-02/06-0 host sp'ace ii 55 ? 55 ? 8 7 5 4 1 2 3 ch. a tx/rxa tx/rxa 55 ? 55 ? 8 7 5 4 1 2 3 ch. b tx/rxb tx/rxb rtad4-rtad0 rt address, parity rtadp d15-d0 +5v -12v/-15v clk in 16 mhz clock oscillator address decoder select mem/reg reset +5v mstclr ssflag/ext_trig int cpu interrupt request cpu d15-d0 ram 64k x 16 max wr oe cs memwr memoe rd/wr rd/wr dtreq dtgrt dtack a15-a0 address decoder memena-in en memena-out transparent/buffered +5v strbd readyd tag_clk cpu strobe cpu acknowledge cpu a15-a0 figure 12. 16-bit direct memory access (dma) mode
29 data device corporation www.ddc-web.com bu-63825 c-02/06-0 host sp'ace ii 55 ? 55 ? 8 7 5 4 1 2 3 ch. a tx/rxa tx/rxa 55 ? 55 ? 8 7 5 4 1 2 3 ch. b tx/rxb tx/rxb rtad4-rtad0 rt address, parity rtadp d15-d0 +5v -12v/-15v clk in 16 mhz clock oscillator address decoder reset +5v mstclr ssflag/ext_trig int cpu interrupt request cpu d15-d0 ram 64k x 16 max wr oe cs rd/wr rd/wr dtreq dtgrt dtack a15-a0 memena-in memena-out transparent/buffered +5v strbd readyd tag_clk memwr memoe cpu a15-a0 +5v 1553 ram select 1553 reg select mem/reg select cpu strobe cpu acknowledge figure 13. 16-bit dma mode with external logic to reduce processor access time to external ram
30 data device corporation www.ddc-web.com bu-63825 c-02/06-0 host sp'ace ii 55 ? 55 ? 8 7 5 4 1 2 3 ch. a tx/rxa tx/rxa 55 ? 55 ? 8 7 5 4 1 2 3 ch. b tx/rxb tx/rxb rtad4-rtad0 rt address, parity rtadp d15-d8 +5v -12v/-15v clk in 16 mhz clock oscillator polarity_sel (note 3) zero_wait (note 4) address decoder select mem/reg rd/wr strbd readyd tag_clk rd/wr cpu strobe cpu acknowledge (note 6) reset notes: +5v mstclr ssflag/ext_trig int cpu interrupt request transfers are triggered by the most significant byte transfer read accesses and by the least significant byte transfer for write accesses. if trigger_sel = "0", then internal 16-bit transfers are triggered by the least significant byte transfer for read accesses and by the most significant byte transfer for write accesses. for zero wait interface (zero wait = "0"): if trigger_sel = "1", then internal 16-bit transfers are triggered by the least significant byte transfer, for both read and write accesses. if trigger_sel = "0", then internal 16-bit transfers are triggered by the most significant byte transfer, for both read and write accesses. 6. cpu acknowledge processor input only for non-zero wait type of interface. 1. cpu d7-d0 connects to both d15-d8 and d7-d0. 2. cpu address latch signal provided by processors with multiplexed address/data buffers. 3. if polarity_sel = "1", then msb/lsb selects the most significant byte when low, and the least significant byte when high. if polarity_sel = "0", then msb/lsb selects the least significant byte when low, and the most significant byte when high. 4. zero wait should be strapped to logic "1" for non-zero wait interface and to logic "0" for zero wait interface. 5. operation of trigger_select input is as follows: for non-zero wait interface (zero wait = "1"): if trigger_sel = "1", then internal 16-bit a15-a14 a13-a0 n/c addr_lat cpu address latch (note 1) 16/8_bit transparent/buffered +5v cpu d7-d0 (note 2) a14-a1 cpu a14-a0 msb/lsb cpu a0 trigger_sel (note 5) d7-d0 figure 14. 8-bit buffered mode
31 data device corporation www.ddc-web.com bu-63825 c-02/06-0 select msb/lsb mem/reg a15-a0 address_lat select msb/lsb mem/reg a15-a0 (1) (2) (3) (4) (1) (2) (3) (4) (5) t1 internal values input signals t2 t4 t5 t3 figure 15. address latch timing notes for figure 15 and associated table. 1. applicable to buffered mode only. address, select and mem/reg latches are always transparent in the transparent mode of operation. 2. latches are transparent when addr_lat is high. internal values do not update when addr_lat is low. 3. msb/lsb input signal is applicable to 8-bit mode only (16/8 input = logic ?0?). msb/lsb input is a ?don?t care? for 16-bit oper ation. ns 20 input hold time following falling edge of addr_lat t5 ns 10 input setup time prior to falling edge of addr_lat t4 ns 10 propagation delay from external input signals to internal signals valid t3 ns 10 addr_lat high delay to internal signals valid t2 ns 20 addr_lat pulse width t1 units max typ min description ref table for figure 15. address latch timing
32 data device corporation www.ddc-web.com bu-63825 c-02/06-0 clock in valid t7 t3 t8 t11 t13 t15 valid t10 t4 t9 t12 t19 valid t16 t17 select (note 2,7) (note 2) (note 3,4,7) (note 4,5) strbd mem/reg rd/wr ioen (note 2,6) (note 6) readyd a15-a0 (note 7, 8) d15-d0 (note 6) t5 t1 t2 t6 t14 t18 figure 16. cpu reading ram (shown for 16-bit, buffered, nonzero wait mode, uncontended access)
33 data device corporation www.ddc-web.com bu-63825 c-02/06-0 ns 0 strbd high hold time from read yd rising t18 ns 50 clock_in rising edge delay to output data valid t19 ns 40 strbd rising delay to output data tri-state t17 ns 0 output data hold time following strbd rising edge t16 note 6 ns 40 strbd rising edge delay to ioen rising edge and read yd rising edge t15 ns read yd falling to strbd rising release time t14 note 6 ns 30 clock in rising edge delay to read yd falling t13 note 2 ns 0 select hold time following ioen falling t6 ns 150 address valid setup time following strbd low (@ 12 mhz) t4 notes 2, 6 notes 2, 6 ns 211.6 strbd low delay to ioen low (uncontended access @ 12 mhz) t2 ns 10 address valid setup time prior to clock in rising edge t9 note 6 ns 455 437.5 420 ioen falling delay to read yd falling (reading ram @ 16 mhz) t11 note 6 ns 205 187.5 170 ioen falling delay to read yd falling (reading registers @ 16 mhz) t11 note 6 ns 600 583.3 565 ioen falling delay to read yd falling (reading ram @ 12 mhz) t11 notes 3, 4, 5 ns 25 mem/reg , rd/wr hold time prior to clock in falling edge t8 note 6 ns 54 output data valid prior to read yd falling (@ 12 mhz) t12 note 6 ns 33 output data valid prior to read yd falling (@ 16 mhz) t12 note 6 ns 265 250 230 ioen falling delay to read yd falling (reading registers @ 12 mhz) t11 note 9 ns 25 address hold time following clock in rising edge t10 notes 3, 4, 5 ns 10 mem/reg , rd/wr setup time prior to clock in falling edge t7 ns 30 clock in rising edge delay to ioen falling edge t5 ns 110 address valid setup time following strbd low (@ 16 mhz) t4 ns 100 mem/reg , rd/wr setup time following strbd low(@ 12 mhz) t3 ns 70 mem/reg , rd/wr setup time following strbd low(@ 16 mhz) t3 notes 2, 6 s 5.3 strbd low delay to ioen low (contended access @ 16 mhz) t2 notes 2, 6 ns 170 strbd low delay to ioen low (uncontended access @ 16 mhz) t2 note 2 ns 15 select and strbd low setup time prior to clock rising edge t1 note reference units max typ min description ref s 7.05 strbd low delay to ioen low (contended access @ 12 mhz) t2 table for figure 16. cpu reading ram or registers (shown for 16-bit, buffered, nonzero wait mode) notes for figure 16 and associated table. 1. for the 16-bit buffered configuration, the inputs trigger_sel and msb/lsb may be connected to +5 v or gnd. for the nonzero wait interface zer o w ait , must be connected to logic ?1?. 2. select and strbd may be tied together. ioen goes low on the second rising clk edge when strbd is sampled low, provided select is also sampled low on that clk edge and the bu- 63825/925?s protocol/memory management logic is not accessing internal ram. if the protocol/memory management logic is access- ing internal ram, select is latched on the second rising clk edge and transfer will begin once protocol/memory management access is complete. if select is sampled high on the second ris- ing clk edge, no transfer will take place. ioen will not drop. 3. mem/reg must be presented high for memory access, low for register access. 4. mem/reg and rd/wr are buffered transparently until the first falling edge of clk after ioen goes low. after this clk edge, mem/reg and rd/wr become latched internally. 5. the logic sense for rd/wr in the diagram assumes that polari- ty_sel is connected to logic "1". if polarity_sel is connected to logic "0", rd/wr must be asserted low to read. 6. the timing for ioen , read yd and d15-d0 assumes a 50 pf load. for loading above 50 pf, the validity of ioen , read yd , and d15- d0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. timing for a15-a0 assumes addr-lat is connected to logic ?1?. refer to address latch timing for additional details. 8. internal ram is accessed by a13 through a0. registers are accessed by a4 through a0. 9. the address bus a15-a0 is internally buffered transparently until the first rising edge of clk after ioen , goes low. after this clk edge, a15-a0 become latched internally.
34 data device corporation www.ddc-web.com bu-63825 c-02/06-0 clock in t1 t6 t7 t2 t3 t18 t16 valid t8 t9 t14 t15 t17 valid t12 t10 t4 t11 t5 valid t13 select (note 2,7) (note 2) (note 3,4,7) (note 4,5) strbd mem/ reg rd/ wr ioen (note 2,6) (note 6) (notes 8, 9) (notes 7,8,9) readyd a15-a0 d15-d0 figure 17. cpu writing ram (shown for 16-bit, buffered, nonzero wait mode, uncontended access)
35 data device corporation www.ddc-web.com bu-63825 c-02/06-0 notes for figure 17 and associated table. 1. for the 16-bit buffered configuration, the inputs trigger_sel and msb/lsb may be connected to +5 v or gnd. for the nonzero wait interface, zer o w ait must be connected to logic ?1.? 2. select and strbd may be tied together. ioen goes low on the second rising clk edge when strbd is sampled low, provided select is also sampled low on that clk edge and the bu- 63825/925?s protocol/memory management logic is not accessing internal ram. if the protocol/memory management logic is access- ing internal ram, select is latched on the second rising clk edge and transfer will begin once protocol/memory management access is complete. if select is sampled high on the second ris- ing clk edge, no transfer will take place. ioen will not drop. 3. mem/reg must be presented high for memory access, low for reg- ister access. 4. mem/reg and rd/wr are buffered transparently until the first falling edge of clk after ioen goes low. after this clk edge, mem/reg and rd/wr become latched internally. 5. the logic sense for rd/wr in the diagram assumes that polari- ty_sel is connected to logic ?1?. if polarity_sel is connected to logic "0", rd/wr must be asserted high to read. 6. the timing for the ioen and read yd outputs assumes a 50 pf load. for loading above 50 pf, the validity of ioen and read yd is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. timing for a15-a0 assumes addr-lat is connected to logic ?1?. refer to address latch timing for additional details. 8. internal ram is accessed by a13 through a0. registers are accessed by a4 through a0. 9. the address bus a15-a0 and data bus d15-d0 are internally buffered transparently until the first rising edge of clk after ioen goes low. after this clk edge, a15-a0 and d15-d0 become latched internally. ns 0 strbd high hold time following read yd rising t18 ns 40 strbd rising delay to ioen rising, read yd rising t17 ns read yd falling to strbd rising release time t16 ns 30 clock in rising edge delay to read yd falling edge t15 note 2 ns 0 select hold time following ioen falling edge t7 ns 150 address valid setup following strbd low (@ 12 mhz) t4 ns 211.6 strbd low delay to ioen low (uncontended access @ 12 mhz) t2 ns 10 address valid setup prior to clock in rising edge t10 ns 10 input data valid setup prior to clock in rising edge t11 note 9 ns 25 input data valid hold time following clock in rising edge t13 note 9 ns 25 address hold time following clock in rising edge t12 notes 3, 4, 5 ns 25 mem/reg , rd/wr hold time following clock in falling edge t9 note 6 note 6 ns ns 265 205 250 187.5 230 170 ioen falling delay to read yd falling (@ 12 mhz) ioen falling delay to read yd falling (@ 16 mhz) t14 t14 notes 3, 4, 5 ns 10 mem/reg , rd/wr setup time prior to clock in falling edge t8 ns ns ns 30 150 110 clock in rising edge delay to ioen falling edge input data valid setup following strbd low (@ 12 mhz) input data valid setup following strbd low (@ 16 mhz) t6 t5 t5 ns 110 address valid setup following strbd low (@ 16 mhz) t4 ns 100 mem/reg and rd/wr setup time following strbd (@ 12 mhz) t3 ns 70 mem/re g and rd/wr setup time following strbd (@ 16 mhz) t3 notes 2, 6 s 5.3 strbd low delay to ioen low (contended access @ 16 mhz) t2 notes 2, 6 ns 170 strbd low delay to ioen low (uncontended access @ 16 mhz) t2 note 2 ns 15 select and strbd low setup time prior to clock in rising edge t1 note reference units max typ min description symbol s 7.05 strbd low delay to ioen low (contended access @ 12 mhz) t2 table for figure 17. cpu writing ram or registers (shown for 16-bit, buffered, nonzero wait mode)
36 data device corporation www.ddc-web.com bu-63825 c-02/06-0 interface to mil-std-1553 bus figure 18 illustrates the interface from the various versions of the sp?ace ii series terminals to a 1553 bus. the figure also indi- cates connections for both direct (short stub) and transformer (long stub) coupling, plus the peak-to-peak voltage levels that appear at various points (when transmitting). table 33 lists the characteristics of the required isolation trans- formers for the various sp?ace ii terminals, the ddc and beta transformer technology corporation corresponding part num- ber, and the mil (desc) drawing number (if applicable). beta transformer technology corporation is a direct subsidiary of ddc. for both coupling configurations, the isolation transformer is the transformer that interfaces directly to the sp?ace ii component. for the transformer (long stub) coupling configuration, the trans- former that interfaces the stub to the bus is the coupling trans- former. the turns ratio of the isolation transformer varies, depending upon the peak-to-peak output voltage of the specific sp?ace ii terminal. the transmitter voltage of each model of the bu-63825 varies directly as a function of the power supply voltage. the turns ratios of the respective transformers will yield a secondary volt- age of approximately 28 volts peak-to-peak on the outer taps (used for direct coupling) and 20 volts peak-to-peak on the inner taps (used for stub coupling). in accordance with mil-std-1553b, the turns ratio of the cou- pling transformer is 1.0 to 1.4. both coupling configurations require an isolation resistor to be in series with each leg con- necting to the 1553 bus; this protects the bus against short cir- cuit conditions in the transformers, stubs, or terminal compo- nents. table 33. isolation transformer guide b-2388 m21038/27 -13, b-2344, m21038/27 -18 bus-29854 1:0.83 surface mount b-2387 m21038/27 -12, m21038/27 -17 lpb-5002 lpb-5009 lpb-6002 lpb-6009 lpb-5001 lpb-5008 lpb-6001 lpb-6008 recommended xformer plug-in bus-25679, b-2203, m21038/27 -02 b-2204, m21038/27 -03 xformer coupled 2:1 1:0.67 1.25:1 (note 5) bu-63825x2 1.4:1 bu-63825x1 direct coupled sp?ace ii part number turns ratio notes for table 33 and figure 18: (1) shown for one of two redundant buses that interface to the bu- 63825 (2) transmitted voltage level on 1553 bus is 6 vp-p min, 7 vp-p nomi- nal, 9 vp-p max. (3) required tolerance on isolation resistors is 2%. instantaneous power dissipation (when transmitting) is approximately 0.5 w (typ), 0.8 w (max). (4) transformer pin numbering is correct for the ddc (e.g., bus- 25679) transformers. for the beta transformers (e.g., b-2203) or the qpl-21038-31 transformers (e.g., m21038/27-02), the winding sense and turns ratio are mechanically the same, but with reversed pin numbering; therefore, it is necessary to reverse pins 8 and 4 or pins 7 and 5 for the beta or qpl transformers (note: ddc trans- former part numbers begin with a bus- prefix, while beta trans- former part numbers begin with a b- prefix). (5) the b-2204, b-2388, and b-2344 transformers have a slightly differ- ent turns ratio on the direct coupled taps then the turns ratio of the bus-29854 direct coupled taps. they do, however, have the same transformer coupled ratio. for transformer coupled applications, either transformer may be used. the transceiver in the bu-63825 was designed to work with a 1:0.83 ratio for direct coupled applica- tions. for direct coupled applications, the 1.20:1 turns ration is rec- ommended, but the 1.25:1 may be used. the 1.25:1 turns ratio will result in a slightly lower transmitter amplitude. (approximately 3.6% lower) and a slight shift in the sp?ace ii's receiver threshold. see table 34 1:2.5 1:1.79 bu-63825 x3/x6
37 data device corporation www.ddc-web.com bu-63825 c-02/06-0 transformer considerations for bu-63825x3 (+5v only versions) in selecting isolation transformers to be used for the bu- 63825x3 (+5v only) versions, there is a limitation on the maxi- mum amount of leakage inductance. if this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by mil- std-1553. in addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifi- cations. the maximum allowable leakage inductance is 6.0 h, and is measured as follows: the side of the transformer that connects to the hybrid is defined as the ?primary? winding. if one side of the primary is shorted to the primary center-tap, the inductance should be measured across the ?secondary? (stub side) winding. this inductance must be less than 6.0 h. similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured across the ?secondary? (stub side) winding must also be less than 6.0 h. the difference between these two measurements is the ?differential? leakage inductance. this value must be less than 1.0 h. beta transformer technology corporation (bttc), a subsidiary of ddc, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct cou- pled, and 1:1.79 transformer coupled. table 33 provides a listing of many of these transformers. for further information, contact bttc at 631-244-7393 or at www.bttc-beta.com. lpb-5015 tlp-1005 hlp-6015 dual epoxy transformer, side by side, surface mount, 0.930" x 0.630", 0.155" max height single metal transformer, hermetically sealed, surface mount, 0.630" x 0.630", 0.175" max height tlp-1105 hlp-6014 dual epoxy transformer, side by side, flat pack, 0.930" x 0.630", 0.155" max height single metal transformer, hermetically sealed, flat pack, 0.630" x 0.630", 0.175" max height tlp-1205 dual epoxy transformer, side by side, through-hole, 0.930" x 0.630", 0.155" max height tst-9027 dual epoxy transformer, twin stacked, flat pack, 0.625" x 0.625", 0.280" max height tst-9017 dual epoxy transformer, twin stacked, surface mount, 0.625" x 0.625", 0.280" max height tst-9007 b-3819 lpb-5014 single epoxy transformer, surface mount, hi-temp solder, 0.625" x 0.625", 0.220" max height. single epoxy transformer, flat pack, 0.625" x 0.625", 0.150" max height b-3227 single epoxy transformer, surface mount, 0.625" x 0.625", 0.275" max height b-3231 single epoxy transformer, flat pack, 0.625" x 0.625", 0.275" max height b-3818 b-3067 b-3226 single epoxy transformer, through-hole, 0.625" x 0.625", 0.220" max height single epoxy transformer, through-hole, 0.625" x 0.625", 0.250" max height bttc part no. transformer configuration single epoxy transformer, surface mount, 0.625" x 0.625", 0.150" max height table 34. bttc transformers for use with bu-63825x3/x6 b-3229 single epoxy transformer, through hole, transformer coupled only, 0.500? x 0.350?, 0.250? max height. dual epoxy transformer, twin stacked, 0.625" x 0.625", 0.280" max height
38 data device corporation www.ddc-web.com bu-63825 c-02/06-0 bu-63825x1 bu-63 9 25x1 data bus z 0 (70 to 85 55 ? 55 ? 1.4:1 3 9 vpp 28 vpp 1 ft max 2:1 3 9 vpp 20 vpp 1 8 3 4 1:1.4 coupling transformer isolation transformer isolation transformer 0.75 z 0 0.75 z 0 transformer coupled (long stub) 20 ft max 28 vpp direct coupled (short stub) or coupling transformer isolation transformer isolation transformer direct coupled (short stub) bu-63825x2 bu-63 9 25x2 55 ? 55 ? 1:0.83 33 vpp 28 vpp 1 ft max 1:0.67 33 vpp 20 vpp 1 8 3 4 1:1.4 0.75 z 0 0.75 z 0 transformer coupled (long stub) 20 ft max 28 vpp or coupling transformer isolation transformer isolation transformer direct coupled (short stub) bu-63825x3 bu-63 9 25x3 bu-63825x6 bu-63 9 25x6 55 ? 55 ? 1:2.5 11.6 vpp 28 vpp 1 ft max 1:1.7 9 11.6vpp 20 vpp 1 8 3 4 1:1.4 0.75 z 0 0.75 z 0 transformer coupled (long stub) 20 ft max 28 vpp or z 0 +5v -15v ?) +5v -12v +5v (70 to 85 ?) figure 18. interface to a 1553 bus
39 data device corporation www.ddc-web.com bu-63825 c-02/06-0 memory write or zero wait state. in transparent mode, active low output signal (memwr ) will be asserted low during memo- ry write transfers to strobe data into internal or external ram (normally connected to the wr signal on external ram chips). in buffered mode, input signal (zer o w ait ) will be used to select between the zero wait mode (zer o w ait = logic 0) and the nonzero wait mode (zer o w ait = logic 1). 30 memwr (o) /zer o_w ait (i) memory output enable or address latch. in transparent mode, memoe output will be used to enable data outputs for exter- nal ram read cycles (normally connected to the oe signal on external ram chips). in buffered mode, addr_lat input will be used to configure the internal address latches in latched mode (when low) or transparent mode (when high). 29 memoe (o)/ addr_lat (i) memory enable input or trigger select. in transparent mode, memena_in is an active low chip select (cs ) input to the 16k x 16 of internal shared ram. when only using internal ram, connect directly to memena_out or ground. in 8-bit buffered mode, the input signal (trigger_sel) indicates the order of byte pairs transferred to or from the bu-63825 by the host processor. this signal has no operation (can be n/c) in the 16-bit buffered mode. in the 8-bit buffered mode, trigger_sel should be asserted high (logic 1) if the byte order for both read operations and write operations is msb followed by lsb. trigger_sel should be asserted low (logic 0) if the byte order for both read operations and write operations is lsb fol- lowed by msb. 33 memena-in (i) /trigger_sel (i) memory enable output. asserted low during both host processor and 1553 protocol/memory management memory transfer cycles. used as a memory chip select (cs ) signal for external ram in the transparent mode. 28 memena-out (o) data transfer acknowledge or polarity select. in transparent mode, active low output signal used to indicate acceptance of the processor interface bus in response to a data transfer grant (dtgr ). in 16-bit buffered mode (transparent/b uffered = logic 0 and 16/8 = logic 1), input signal used to control the logic sense of the rd/wr signal. when polarity_sel is logic 1, rd/wr must be asserted high (logic 1) for a read operation and low (logic 0) for a write operation. when polarity_sel is logic 0, rd/wr must be asserted low (logic 0) for a read operation and high (logic 1) for a write operation. in 8-bit buffered mode (transparent/b uffered = logic 0 and 16/8 = logic 0), input signal used to con- trol the logic sense of the msb/lsb signal. when polarity_sel is logic 0, msb/lsb must be asserted low (logic 0) to indi- cate the transfer of the least significant byte and high (logic 1) to indicate the transfer of the most significant byte. when polarity_sel is logic 1, msb/lsb must be asserted high (logic 1) to indicate the transfer of the least significant byte and low (logic 0) to indicate the transfer of the most significant byte. 32 dt a ck (o)/ polarity_sel (i) data transfer grant or most significant byte/least significant byte. in transparent mode, active low input signal asserted, in response to the dtreq output, to indicate that access to the processor buses has been granted to the bu-63825. in 8-bit buffered mode, input signal used to indicate which byte is being transferred (msb or lsb). the polarity_sel input con- trols the logic sense of msb/lsb. (note: only the 8-bit buffered mode uses msb/lsb.) see description of polarity_sel signal. 26 dtgr t (i) /msb/lsb (i) data transfer request or 16-bit/8-bit transfer mode select. in transparent mode, active low output signal used to request access to the processor interface bus (address, data, and control buses). in buffered mode, input signal used to select between the 16-bit data transfer mode (16/8 = logic 1) and the 8 bit data transfer mode (16/8 = logic 0). 31 dtreq (o) /16/8 (i) interrupt request output. if the level/pulse interrupt bit (bit 3) of configuration register #2 is low, a negative pulse of approximately 500 ns in width is output on int . if bit 3 is high, a low level interrupt request output will be asserted on int. 65 int (o) handshake output to host processor. for a nonzero wait state read access, signals that data is available to be read on d15 through d0. for a nonzero wait state write cycle, signals the completion of data transfer to a register or ram location. in the buffered zero wait state mode, active high output signal (following the rising edge of strbd used to indicate the latching of address and data (write only) and that an internal transfer between the address/data latches and the ram/registers is on-going. 66 read yd (o) tri-state control for external address and data buffers. generally not needed in the buffered mode. when low, external buffers should be enabled to allow the host processor access to the bu-63825?s ram and registers. 67 ioen (o) read/write. for host processor access, selects either reading or writing. in the 16-bit buffered mode, if polarity select is logi c (0), then rd/wr is low (logic 0 ) for read accesses and high (logic 1) for write accesses. if polarity select is logic 1 or the con- figuration of the interface is a mode other than 16-bit buffered mode, then rd/wr is high (logic 1 ) for read accesses and low (logic 0) for write accesses. 6 rd/wr (i) memory/register. generally connected to either a cpu address line or address decoder output. selects between memory access mem/reg = 1 (or register access mem/reg = 0 ). 5 mem/reg (i) generally connected to a cpu address decoder output to select the bu-63825 for a transfer to/from either ram or register. may be tied to strbd 3 select (i) strobe data. used with select to initiate and control the data transfer cycle between the host processor and the bu-63825. 4 strbd (i) used to select between the transparent/ dma mode (when strapped to logic 1) and the buffered mode (when strapped to logic 0) for the host processor interface. 64 transparent/ b uffered (i) description pin signal name table 35. signal descriptions, processor/memory interface and control (15)
40 data device corporation www.ddc-web.com bu-63825 c-02/06-0 external time tag clock input. use may be designated by bits 7, 8, and 9 of configuration register #2. when used it increments the internal time tag register/counter. if not used, should be connected to +5v or ground. 63 tag_clk (i) subsystem flag or external trigger input. in the remote terminal mode, asserting this input will set the subsystem flag bit in the bu-63825?s rt status word. a low on the ssfla g input overrides a logic ?1? of the respective bit (bit 8) of configuration register #1. in the bus controller mode, an enabled external bc start option (bit 7 of configuration register #1) and a low-to-high transition on this input will issue a bc start command, starting execution of the current bc frame. in the word monitor mode, an enabled external trigger (bit 7 of configuration register #1) and a low-to-high transition on this input will issue a monitor trigger. 27 ssfla g (i)/ ext_trig (i) in command. in bc mode, asserted low throughout processing cycle for each message. in rt mode or message monitor mode, asserted low following receipt of command word and kept low until completion of current message sequence. in word monitor mode, goes low following monitor start command, kept low while monitor is on-line, goes high following reset command. 45 incmd (o) master clear. negative true reset input, normally asserted low following power turn-on. requires a minimum 100ns neg- ative pulse to reset all internal logic to its ?power turn-on? state. 7 mstclr (i) 16mhz (or 12mhz) clock input. 19 clock in (i) description pin signal name table 38. signal descriptions, power and ground (8) -vb ground 37 - gnd ch. b +5v supply 38 - ch. b -15v(-12v) supply 36 - +5vb ground 69 - gnd ch. a +5v supply 68 - +5va ch. a -15v(-12v) supply 70 - -va ground 18 18 gnd logic +5v supply 54 54 +5v logic description x1/x2* x0* pin pin signal name table 37. signal descriptions, rt address (6) rtadp (i) remote terminal address parity. must provide odd parity sum with rtad4-rtad0 in order for the rt to respond to non- broadcast commands. 44 39 rtad0 (lsb) (i) 40 rtad1 (i) remote terminal address inputs 41 rtad2 (i) 42 rtad3 (i) 43 rtad4 (msb) (i) description pin signal name table 36. signal descriptions, miscellaneous (5) note: *pin x0, x1/x2, x3, x6 refer to package option(x) and voltage transceiver option (0, 1, 2, 3, 6). see ordering information. 37 37 38 38 - - 69 69 68 68 - - 18 18 54 54 x6* x3* pin pin
41 data device corporation www.ddc-web.com bu-63825 c-02/06-0 16-bit bidirectional address bus. in both the buffered and transparent modes, the host cpu accesses the bu-63825 registers and 16k words of internal ram by a13 through a0. the host cpu performs register selection by a4 through a0. in the buffered mode, a15-a0 are inputs only. in the transparent mode, a15-a0 are inputs during cpu accesses and drive outward (towards the cpu) when the 1553 protocol/memory management logic accesses up to 64k x 16 of external ram. the address bus drives outward only in the transparent mode when the signal dt a ck is low (indicating that the 63825 has control of the processor interface bus) and ioen is high (indicating that this is not a cpu access). most of the time, including imme- diately after power turn-on reset, the a15-a0 outputs will be in their disabled (high impedance) state. 25 a10 a00 24 a01 23 a02 22 a03 a04 21 20 a05 17 a06 16 a07 15 a08 14 13 a09 12 a11 11 a12 10 a13 9 a14 8 a15 (msb) description pin signal name table 40. signal descriptions, address bus (16) signal name pin description tx/rx-a (i/o) - pin tx/rx -a (i/o) - 1 tx/rx-b (i/o) - 2 tx/rx -b (i/o) - analog transmit/receive input/outputs. connect directly to 1553 isolation transformers. 34 35 x0* x1/x2* note: *pin x0, x1/x2, x3, x6 refer to package option(x) and voltage transceiver option (0, 1, 2, 3, 6). see ordering information. pin 1 2 34 35 x3* pin 1 2 34 35 x6* table 39. signal descriptions, 1553 isolation transformer interface (4)
42 data device corporation www.ddc-web.com bu-63825 c-02/06-0 - - tx_inh_b_in transmitter inhibit inputs for the channel a and channel b mil-std-1553 transmitters. for normal operation, these inputs should be connected to logic "0". to force a shutdown of channel a and/or channel b, a value of logic "1" should be applied to the respective tx_inh input. digital manchester biphase receive data inputs. connect directly to corresponding outputs of a mil- std-1553 or mil-std-1773 transceiver. - - tx_inh_a_in - - 34 35 rxb rxb digital manchester biphase transmit data outputs. connect directly to corresponding inputs to a mil- std-1553 or mil-std-1773 (fiber optic) transceiver. - 2 - 37 - 69 rxa txb txa - 1 - 38 - 70 rxa txb txa description x1/x2* pin x0* pin signal name note: *pin x0, x1/x2, x3, x6 refer to package option(x) and voltage transceiver option (0, 1, 2, 3, 6). see ordering information. - - - - - - - - - - x3* pin 36 70 - - - - - - - - x6* pin - - n/c no user connections - - n/c 70 36 - - 16-bit bidirectional data bus. this bus interfaces the host processor to the internal registers and 16k words of ram. in addition, in the transparent mode, this bus allows data transfers to take place between the internal protocol/memory man- agement logic and up to 64k x 16 of external ram. most of the time, the outputs for d15 through d0 are in their high impedance state. they drive outward in the buffered or transparent mode when the host cpu reads the internal ram or registers. or, in the transparent mode, when the protocol/memory management logic is accessing (either reading or writ- ing) internal ram or writing to external ram. 46 d10 d00 47 d01 48 d02 49 d03 d04 50 51 d05 52 d06 53 d07 55 d08 56 57 d09 58 d11 59 d12 table 41. signal descriptions, data bus (16) 60 d13 61 d14 62 d15 (msb) description pin signal name table 42. signal descriptions, transmitter/receivers (14) - 36 tx_inh_b_out digital transmit inhibit outputs. connect to tx_inh_out inputs of a mil-std-1553 transceiver. asserted high to inhibit when not transmitting on the respective bus. - 68 tx_inh_a_out - - - -
43 data device corporation www.ddc-web.com bu-63825 c-02/06-0 table 43. bu-63825 pin listing (70-pin dip, flat pack) pin x1, x2 x0 pin signal name 24 21 16 8 17 12 4 22 19 14 6 10 2 23 20 15 7 11 3 18 13 5 9 1 a01 a04 a07 a15 a06 a11 strbd a03 clock_in a09 rd/wr a13 tx/rx-a rxa a02 a05 a08 mstclr a12 select gnd a10 mem/reg a14 tx/rx-a rxa 69 64 56 65 60 52 70 67 62 54 58 50 68 63 55 59 51 66 61 53 57 49 gnd txa transparent/b uffered d09 int d13 d06 -va (note 2) txa ioen d15 +5v logic d11 d04 +5va tx_inh_out_a tag_clk d08 d12 d05 read yd d14 d07 d10 d03 notes: 1) pin x0, x1/x2, x3, x6 refer to package option(x) and voltage transceiver option (0, 1, 2, 3, 6). see ordering information. 2) -15v for bu-63825x1 -12v for bu-63825x2. x3 x6 signal name x1, x2 x0 x3 x6 n/c tx_inh_in_a 32 28 30 34 26 31 35 27 29 33 25 dt a ck /polarity_sel memena_out memwr /zer o_w ait tx/rx-b rx-b dtgr t /msb/lsb dtreq /16/8 tx/rx-b rx-b ssfla g /ext_trig memoe /addr_lat memena_in /trigger_sel a00 48 45 40 41 36 46 43 38 47 44 39 42 37 d02 incmd rtad1 rtad2 -vb (note 2) tx_inh_out_b d00 rtad4 +5vb txb d01 rtadp rtad0 rtad3 txb gnd n/c tx_inh_in_b
44 data device corporation www.ddc-web.com bu-63825 c-02/06-0 1.000 max (25.4) 0.400 (10.16) 1.700 (43.18) index denotes pin 1 0.215 (5.46) max notes: 1. dimensions are in inches (millimeters). 2. package material: alumina (al 2 o 3 ). 3. lead material: kovar, plated by 150 minimum nickel, plated by 50 minimum gold. 1.900 max (48.26) 0.180 0.010 typ (4.57 0.25) 0.100 (2.54) 0.100 (2.54) typ 0.050 (1.27) typ 0.600 (15.24) 0.018 0.002 dia typ (0.46 0.05) 34 35 36 37 69 70 2 top view bottom view index denotes pin 1 1.900 (48.26) max side view figure 19. bu-63825dx, 70-pin dip ceramic mechanical outline
45 data device corporation www.ddc-web.com bu-63825 c-02/06-0 70 36 35 1 0.018 0.002 dia typ (0.46 0.05) 1.900 max (48.26) 34 eq sp @ 0.050 = 1.700 tol noncum 0.050 (typ) (1.27) index denotes pin 1 1.000 max (25.4) 0.215 (5.46) max 0.010 0.002 typ (0.254 0.051) 0.070 0.010 (1.78) pin numbers for ref only top view side view notes: 1. dimensions are in inches (millimeters). 2. package material: alumina (al 2 o 3 ). 3. lead material: kovar, plated by 150 minimum nickel, plated by 50 minimum gold. 1.760 0.020 (44.70) 0.100 max (2.54) 0.405 min (typ) (10.29) 0.595 max (typ) (15.11) ceramic bar (2 places) 0.035 (typ) (0.89) 1.024 max (26.0) 0.012 max (0.31) figure 20. bu-63825fx, 70-pin flat pack ceramic mechanical outline
46 data device corporation www.ddc-web.com bu-63825 c-02/06-0 70 36 35 1 1.000 max (25.4) 1.900 max (48.26) 0.018 0.002 (0.46 0.05) pin 1 denoted by index mark 0.050 typ (1.27) 34 eq. sp. @ 0.050 = 1.700 ( 1.27 = 43.18) (tol. noncum) pin numbers are for ref. only 0.080 min (2.032) 0.190 0.010 (4.826 0.254) 0.040 typ (1.016) 0.050 min (1.27) 0.012 max (0.305) 1.024 max (26.0) 1.38 0.02 (35.05 0.51) 0.065 ref (1.651) 0.010 0.002 (0.254 0.051) 0.215 max (5.461) index denotes pin 1 notes: 1. dimensions are in inches (millimeters). 2. package material: alumina (al 2 o 3 ). 3. lead material: kovar, plated by 150 minimum nickel, plated by 50 minimum gold. top view figure 21. bu-63825gx, 70-pin gull lead ceramic mechanical outline
47 data device corporation www.ddc-web.com bu-63825 c-02/06-0 ordering information bu-63825 xx-xxxx supplemental process requirements: s = pre-cap source inspection l = 100% pull test (standard on this device) q = 100% pull test and pre-cap source inspection k = one lot date code w = one lot date code and pre-cap source inspection y = one lot date code and 100% pull test z = one lot date code, pre-cap source inspection and 100% pull test blank = none of the above other criteria: 0 = no x ray 1 = x ray process requirements: 0 = standard ddc processing, no burn-in 1 = mil-prf-38534 compliant (notes 1 and 3) 2 = b (note 2) 3 = mil-prf-38534 compliant (notes 1 and 3) with pind testing 4 = mil-prf-38534 compliant (notes 1 and 3) with solder dip 5 = mil-prf-38534 compliant (notes 1 and 3)) with pind testing and solder dip 6 = b (note 2) with pind testing 7 = b (note 2) with solder dip 8 = b (note 2) with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data voltage transceiver option: 0 = no transceiver 1 = +5/-15 v 2 = +5/-12 v 3 = +5/+5 v 6 = +5/+5 v with transmit inhibit (tx_inhibit) package: d = dip f = flat pack g = gull leads (above ?process requirements? must include solder dip.) product type: 63825 = 70-pin bc/rt/mt with 16k x 16 internal ram 63925 = 70-pin bc/rt/mt with 16k x 16 internal ram and with rt address latch notes: 1. standard processing on this device includes 320 hours of burn-in and 100% non-destruct pull-test. (see table 3). 2. standard ddc processing with burn-in and full temperature (-55c to +125c) test. 3. mil-prf-38534 product grading is designated with the following dash numbers: class h is a -11x, 13x, 14x, 15x, 41x, 43x, 44x, 45x class g is a -21x, 23x, 24x, 25x, 51x, 53x, 54x, 55x class d is a -31x, 33x, 34x, 35x, 81x, 83x, 84x, 85x 4. these products contain tin-lead solder finish as applicable to solder dip requirements.
the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-15 00 12-11, fax: +49-(0)89-15 00 12-22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u 48 c-02/06-0 printed in the u.s.a. data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u table 1 1015 (note 1) , 1030 (note 2) burn-in notes: 1. for process requirement "b*" (refer to ordering information), devices may be non-compliant with mil- std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing for hybrid and monolithic hermetic products

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